Preliminary W78LE516
- 4 -
BLOCK DIAGRAM
P3.0
P3.7
P1.0
P1.7
ALU
Port 0
Latch
Port 1
Latch
Timer
1
Timer
0
Timer
2
Port
1
UART
XTAL1
PSEN
ALE
VssVCCRSTXTAL2
Oscillator
Interrupt
PSW
Instruction
Decoder
&
Sequencer
Reset Block
Bus & Clock
Controller
SFR RAM
Address
Power control
512 bytes
RAM & SFR
Stack
Pointer
B
Addr. Reg.
Incrementor
PC
DPTR
Temp Reg.
T2T1
ACC
Port 3
Latch
Port 4
Latch
Port
3
Port 2
Latch
P4.0
P4.3
Port
4
Port
0
Port
2
P2.0
P2.7
P0.0
P0.7
64KB
MTP-ROM
4KB
MTP-ROM
FUNCTIONAL DESCRIPTION
The W78LE516 architecture consists of a core controller surrounded by various registers, four general
purpose I/O ports, one special purpose programmable 4-bits I/O port, 512 bytes of RAM, three
timer/counters, a serial port. The processor supports 111 different opcodes and references both a 64K
program address space and a 64K data storage space.
RAM
The internal data RAM in the W78LE516 is 512 bytes. It is divided into two banks: 256 bytes of
scratchpad RAM and 256 bytes of AUX-RAM. These RAMs are addressed by different ways.
•
RAM 0H
−
7FH can be addressed directly and indirectly as the same as in 8051. Address pointers
are R0 and R1 of the selected register bank.