Preliminary W78LE516
Publication Release Date: June 2000
- 21 - Revision A1
Data Read Cycle
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES
ALE Low to
Low
T
DAR
3 T
CP
-
∆
-
3 T
CP+
∆
nS 1, 2
Low to Data Valid
T
DDA
- - 4 T
CP
nS 1
Data Hold from
High
T
DDH
0 - 2 T
CP
nS
Data Float from
High
T
DDZ
0 - 2 T
CP
nS
Pulse Width
T
DRD
6 T
CP
-
∆
6 T
CP
- nS 2
Notes:
1. Data memory access time is 8 TCP.
2. "
∆
" (due to buffer driving delay and wire loading) is 20 nS.
Data Write Cycle
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
ALE Low to
Low
T
DAW
3 T
CP
-
∆
-
3 T
CP
+
∆
nS
Data Valid to
Low
T
DAD
1 T
CP
-
∆
- - nS
Data Hold from
High
T
DWD
1 T
CP
-
∆
- - nS
Pulse Width
T
DWR
6 T
CP
-
∆
6 T
CP
- nS
Note: "
∆
" (due to buffer driving delay and wire loading) is 20 nS.
Port Access Cycle
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Port Input Setup to ALE Low T
PDS
1 TCP - - nS
Port Input Hold from ALE Low T
PDH
0 - - nS
Port Output to ALE T
PDA
1 TCP - - nS
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to
ALE, since it provides a convenient reference.