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W6811IR

W6811IR首页预览图
型号: W6811IR
PDF文件:
  • W6811IR PDF文件
  • W6811IR PDF在线浏览
功能描述: SINGLE-CHANNEL VOICEBAND CODEC
PDF文件大小: 457.22 Kbytes
PDF页数: 共37页
制造商: WINBOND[Winbond]
制造商LOGO: WINBOND[Winbond] LOGO
制造商网址: http://www.winbond.com
捡单宝W6811IR
PDF页面索引
120%
W6811
Publication Release Date: October 23, 2003
- 7 - Revision A10
6. PIN DESCRIPTION
Pin
Name
Pin
No.
V
DD
*
Functionality
V
REF
1 A This pin is used to bypass the on-chip 2.5V voltage reference. It needs to be
decoupled to V
SSA
through a 0.1 µF ceramic decoupling capacitor. No
external loads should be tied to this pin.
RO- 2 A Inverting output of the receive smoothing filter. This pin can typically drive a 2
k load to 1.575 volt peak referenced to the analog ground level.
PAI 3 A This pin is the inverting input to the power amplifier. Its DC level is at the V
AG
voltage.
PAO- 4 A
Inverting power amplifier output. This pin can drive a 300 load to 1.575 volt
peak referenced to the V
AG
voltage level.
PAO+ 5 A
Non-inverting power amplifier output. This pin can drive a 300 load to 1.575
Volt peak referenced to the V
AG
voltage level.
V
DDA
6 A
Analog power supply. This pin should be decoupled to V
SSA
with a 0.1µF
ceramic capacitor.
NC 7 Not Connected
V
DDD
8 D
Digital power supply. This pin should be decoupled to V
SSD
with a 0.1µF
ceramic capacitor. For correct operation, V
DDD
value should always be lower
then V
DDA
.
FSR 9 D 8 kHz Frame Sync input for the PCM receive section. This pin also selects
channel 0 or channel 1 in the GCI and IDL modes. It can also be connected
to the FST pin when transmit and receive are synchronous operations.
PCMR 10 D PCM input data receive pin. The data needs to be synchronous with the FSR
and BCLKR pins.
BCLKR 11 D PCM receive bit clock input pin. This pin also selects the interface mode. The
GCI mode is selected when this pin is tied to V
SSD
. The IDL mode is selected
when this pin is tied to V
DDD
. This pin can also be tied to the BCLKT when
transmit and receive are synchronous operations.
PUI 12 D Power up input signal. When this pin is tied to V
DDD
, the part is powered up.
When tied to V
SSD
, the part is powered down.
MCLK 13 D System master clock input. Possible input frequencies are 256 kHz, 512 kHz,
1536 kHz, 1544 kHz, 2048 kHz, 2560 kHz & 4096 kHz. For a better
performance, it is recommended to have the MCLK signal synchronous and
aligned to the FST signal. This is a requirement in the case of 256 and 512
kHz frequency.
BCLKT 14 D PCM transmit bit clock input pin.
PCMT 15 D PCM output data transmit pin. The output data is synchronous with the FST
and BCLKT pins.
FST 16 D 8 kHz transmit frame sync input. This pin synchronizes the transmit data
bytes.
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