W3EG72255S-D3
-JD3
-AJD3
1
White Electronic Designs
November 2004
Rev. 2
PRELIMINARY*
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
FEATURES
Double-data-rate architecture
DDR200, DDR266 and DDR333:
• JEDEC design specifi cations
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh
Serial presence detect
Dual Rank
Power supply: V
CC =
2.5V ± 0.2V
JEDEC standard 184 pin DIMM package
• Package height options:
JD3: 30.48mm (1.2"),
AJD3: 28.70mm (1.13")
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
DESCRIPTION
The W3EG72255S is a 2x128Mx72 Double Data Rate
SDRAM memory module based on 512Mb DDR SDRAM
components. The module consists of eighteen 256Mx4
stacks, in 66 pin TSOP packages mounted on a 184 pin
FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible
on both edges and Burst Lengths allow the same
device to be useful for a variety of high bandwidth, high
performance memory system applications.
* wThis product is under development, is not qualifi ed or characterized and is subject
to change without notice.
PRELIMINARY*
2GB – 2x128Mx72 DDR SDRAM REGISTERED ECC, w/PLL
OPERATING FREQUENCIES
DDR333 @CL=2.5 DDR266 @CL=2 DDR266 @CL=2 DDR266 @CL=2.5 DDR200 @CL=2
Clock Speed 166MHz 133MHz 133MHz 133MHz 100MHz
CL-t
RCD
-t
RP
2.5-3-3 2-2-2 2-3-3 2.5-3-3 2-2-2