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W3EG2128M64ETSRXXXJD3MG

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型号: W3EG2128M64ETSRXXXJD3MG
PDF文件:
  • W3EG2128M64ETSRXXXJD3MG PDF文件
  • W3EG2128M64ETSRXXXJD3MG PDF在线浏览
功能描述: 2GB - 2x128Mx64 DDR SDRAM REGISTERED w/PLL
PDF文件大小: 308.16 Kbytes
PDF页数: 共13页
制造商: WEDC[White Electronic Designs Corporation]
制造商LOGO: WEDC[White Electronic Designs Corporation] LOGO
制造商网址: http://www.whiteedc.com
捡单宝W3EG2128M64ETSRXXXJD3MG
PDF页面索引
120%
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
April 2005
Rev. 0
W3EG2128M64ETSR-JD3
ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS
Notes 1-5, 7; notes appear following parameter tables; 0°C ≤ T
A
≤ +70°C; V
CC
= +2.5V ±0.2V, V
CCQ
= +2.5V ±0.2V
AC Characteristics 335 263/265
Parameter Symbol Min Max Min Max Units Notes
Access window of DQs from CK, CK# t
AC
-0.7 +0.7 -0.75 +0.75 ns
CK high-level width t
CH
0.45 0.55 0.45 0.55 t
CK
16
CK low-level width t
CL
0.45 0.55 0.45 0.55 t
CK
16
Clock cycle time CL=2.5 t
CK
(2.5) 6 13 7.5 13 ns 22
CL=2 t
CK
(2) 7.5 13 10 13 ns 22
DQ and DM input hold time relative to DQS t
DH
0.45 0.5 ns 14, 17
DQ and DM input setup time relative to DQS t
DS
0.45 0.5 ns 14, 17
DQ and DM input pulse width (for each input) t
DIPW
1.75 1.75 ns 17
Access window of DQS from CK, CK# t
DQSCK
-0.6 +0.6 -0.75 +0.75 ns
DQS input high pulse width t
DQSH
0.35 0.35 t
CK
DQS input low pulse width t
DQSL
0.35 0.35 t
CK
DQS-DQ skew, DQS to last DQ valid, per group, per access t
DQSQ
0.45 0.5 ns 13, 14
Write command to fi rst DQS latching transition t
DQSS
0.75 1.25 0.75 1.25 t
CK
DQS falling edge to CK rising - setup time t
DSS
0.2 0.2 t
CK
DQS falling edge from CK rising - hold time t
DSH
0.2 0.2 t
CK
Half clock period t
HP
t
CH
, t
CL
t
CH
, t
CL
ns 18
Data-out high-impedance window from CK, CK# t
HZ
0.7 0.75 ns 8, 19
Data-out low-impedance window from CK, CK# t
LZ
-0.7 -0.75 ns 8, 20
Address and control input hold time (fast slew rate) t
IHf
0.75 0.90 ns 6
Address and control input set-up time (fast slew rate) t
ISf
0.75 0.90 ns 6
Address and control input hold time (slow slew rate) t
IHs
0.8 1 ns 6
Address and control input setup time (slow slew rate) t
ISs
0.8 1 ns 6
Address and control input pulse width (for each input) t
IPW
2.2 2.2 ns
LOAD MODE REGISTER command cycle time t
MRD
12 15 ns
DQ-DQS hold, DQS to fi rst DQ to go non-valid, per access t
QH
t
HP
- t
QHS
t
HP
- t
QHS
ns 13, 14
Data hold skew factor t
QHS
0.55 0.75 ns
ACTIVE to PRECHARGE command t
RAS
42 72,000 40
120,000
ns 15
ACTIVE to READ with Auto precharge command t
RAP
15 20 ns
ACTIVE to ACTIVE/AUTO REFRESH command period t
RC
60 65 ns
AUTO REFRESH command period t
RFC
120 120 ns 21
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