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W3EG2128M64ETSRXXXJD3MG

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型号: W3EG2128M64ETSRXXXJD3MG
PDF文件:
  • W3EG2128M64ETSRXXXJD3MG PDF文件
  • W3EG2128M64ETSRXXXJD3MG PDF在线浏览
功能描述: 2GB - 2x128Mx64 DDR SDRAM REGISTERED w/PLL
PDF文件大小: 308.16 Kbytes
PDF页数: 共13页
制造商: WEDC[White Electronic Designs Corporation]
制造商LOGO: WEDC[White Electronic Designs Corporation] LOGO
制造商网址: http://www.whiteedc.com
捡单宝W3EG2128M64ETSRXXXJD3MG
PDF页面索引
120%
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
April 2005
Rev. 0
W3EG2128M64ETSR-JD3
ADVANCED
I
DD
SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0°C T
A
70°C, V
CCQ
= 2.5V ± 0.2V, V
CC
= 2.5V ± 0.2V
Includes DDR SDRAM component only
Parameter Symbol Conditions
DDR333@
CL=2.5
Max
DDR266@
CL=2
Max
DDR266@
CL=2.5
Max Units
Operating Current I
DD0
One device bank; Active - Precharge; t
RC
=t
RC
(MIN); t
CK
=t
CK
(MIN); DQ,DM and DQS inputs
changing once per clock cycle; Address and control
inputs changing once every two cycles.
2080 2080 1880 mA
Operating Current I
DD1
One device bank; Active-Read-Precharge Burst
= 2; t
RC
=t
RC
(MIN); t
CK
=t
CK
(MIN); l
OUT
= 0mA;
Address and control inputs changing once per
clock cycle.
2360 2360 2160 mA
Precharge Power-
Down Standby Current
I
DD2P
All device banks idle; Power-down mode; t
CK
=t
CK
(MIN); CKE=(low)
160 160 160 rnA
Idle Standby Current I
DD2F
CS# = High; All device banks idle; t
CK
=t
CK
(MIN);
CKE = high; Address and other control inputs
changing once per clock cycle. V
IN
= V
REF
for DQ,
DQS and DM.
1040 1040 960 mA
Active Power-Down
Standby Current
I
DD3P
One device bank active; Power-Down mode; t
CK
(MIN); CKE=(low)
560 560 480 mA
Active Standby Current I
DD3N
CS# = High; CKE = High; One device bank; Active-
Precharge; t
RC
=t
RAS
(MAX); t
CK
=t
CK
(MIN); DQ, DM
and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once
per clock cycle.
800 800 720 mA
Operating Current I
DD4R
Burst = 2; Reads; Continuous burst; One device
bank active; Address and control inputs changing
once per clock cycle; T
CK
= T
CK
(MIN); l
OUT
= 0mA.
2560 2560 2320 mA
Operating Current I
DD4W
Burst = 2; Writes; Continuous burst; One device
bank active; Address and control inputs changing
once per clock cycle; t
CK
=t
CK
(MIN); DQ,DM and
DQS inputs changing once per clock cycle.
2640 2640 2400 rnA
Auto Refresh Current I
DD5
t
RC
= t
RC
(MIN) 3520 3520 3360 mA
Self Refresh Current I
DD6
CKE 0.2V
144 144 144 mA
Operating Current I
DD7A
Four bank interleaving Reads (BL=4) with auto
precharge with t
RC
=t
RC
(MIN); t
CK
=t
CK
(MIN);
Address and control inputs change only during
Active Read or Write commands.
5000 5000 4600 mA
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