10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
April 2005
Rev. 0
W3EG2128M64ETSR-JD3
ADVANCED
I
DD1
: OPERATING CURRENT : ONE BANK
1. Typical Case : V
CC
=2.5V, T=25°C
2. Worst Case : V
CC
=2.7V, T=10°C
3. Only one bank is accessed with t
RC
(min), Burst
Mode, Address and Control inputs on NOP edge
are changing once per clock cycle. I
OUT
= 0mA
4. Timing Patterns :
• DDR266 (133MHz, CL=2.5) : t
CK=
7.5ns,
CL=2.5, BL=4, t
RCD=
3*t
CK
, t
RC=
9*t
CK
, t
RAS=
5*t
CK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
• DDR333 (166MHz, CL=2.5) : t
CK
=6ns, BL=4,
t
RCD
=10*t
CK
, t
RAS
=7*t
CK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
I
DD7A
: OPERATING CURRENT : FOUR BANKS
1. Typical Case : V
CC
=2.5V, T=25°C
2. Worst Case : V
CC
=2.7V, T=10°C
3. Four banks are being interleaved with t
RC
(min),
Burst Mode, Address and Control inputs on NOP
edge are not changing. Iout=0mA
4. Timing Patterns :
• DDR266 (133MHz, CL=2.5) : t
CK
=7.5ns,
CL=2.5, BL=4, t
RRD
=3*t
CK
, t
RCD
=3*t
CK
Read with Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
• DDR333 (166MHz, CL=2.5) : t
CK
=6ns,
BL=4, t
RRD
=3*t
CK
, t
RCD
=3*t
CK
, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
DETAILED TEST CONDITIONS FOR DDR SDRAM I
DD1
& I
DD7A
Legend:
A = Activate, R = Read, W = Write, P = Precharge, N = NOP
A (0-3) = Activate Bank 0-3
R (0-3) = Read Bank 0-3
