W29EE012
- 18 -
BONDING PAD DIAGRAM
X
Y
4
A12A7
4
5
A14
30
31
#WE A13
29
3
A15 A16
2
1
28
A8
27
A9
10
A2
#CE
23
#OE
25
24
A10
RA8014
15
DQ2
16
GND
13
DQ0
DQ1
14
12
A0
9
A3
A5
6
7
A4
A6
6
GND
17s
-1
17s
-2
GND
21
DQ6
22
DQ7
20
DQ5
18
DQ3
DQ4
19
11
A1
26
A11
32
33s
-2
Vcc Vcc
33s
-1
Vcc
PAD NO.
X Y
1 -187.04 1920.30
2 -380.84 1920.30
3 -517.64 1920.30
4 -1121.73 1920.30
5 -1258.52 1920.30
6 -1484.75 1901.22
7 -1484.75 1713.42
8 -1484.75 1576.62
9 -1453.92 -1577.46
10 -1453.92 -1742.70
11 -1453.92 -1879.50
12 -1240.62 -1923.06
13 -977.19 -1921.98
14 -727.22 -1921.98
15 -504.26 -1921.98
16 -264.72 -1900.20
17S-1 -86.90 -1900.20
17S-2 -1.70 -1900.20
18 286.06 -1909.98
19 509.01 -1909.98
20 758.98 -1909.98
21 981.94 -1909.98
22 1231.90 -1909.98
23 1469.29 -1897.26
24 1468.29 -1708.32
25 1469.29 -1571.52
26 1476.60 1564.62
27 1476.60 1752.42
28 1476.60 1889.22
29 1311.85 1920.30
30 891.00 1920.30
31 523.36 1920.30
32 310.36 1914.24
33S-1 180.16 1914.24
33S-2 94.96 1914.24
Note: For bare chip form (C.O.B.) applications, the substrate must be connected to VDD or left floating in the PCB layout.
