W29EE012
Publication Release Date: March 26, 2002
- 11 - Revision A3
Read Cycle Timing Parameters
(VDD = 5.0V ±10%, VSS = 0V, TA = 0 to 70° C)
PARAMETER SYM. W29EE012 UNIT
MIN. MAX.
Read Cycle Time TRC 150 - nS
Chip Enable Access Time TCE - 150 nS
Address Access Time TAA - 150 nS
Output Enable Access Time TOE - 70 nS
#CE Low to Active Output TCLZ 0 - nS
#OE Low to Active Output TOLZ 0 - nS
#CE High to High-Z Output TCHZ - 45 nS
#OE High to High-Z Output TOHZ - 45 nS
Output Hold from Address Change TOH 0 - nS
Byte/Page-Write Cycle Timing Parameters
PARAMETER SYMBOL
MIN. TYP. MAX. UNIT
Write Cycle (Erase and Program) TWC - - 10 mS
Address Setup Time TAS 0 - - nS
Address Hold Time TAH 50 - - nS
#WE and #CE Setup Time TCS 0 - - nS
#WE and #CE Hold Time TCH 0 - - nS
#OE High Setup Time TOES 10 - - nS
#OE High Hold Time TOEH 10 - - nS
#CE Pulse Width TCP 70 - - nS
#WE Pulse Width TWP 70 - - nS
#WE High Width TWPH 150 - - nS
Data Setup Time TDS 50 - - nS
Data Hold Time TDH 10 - - nS
Byte Load Cycle Time TBLC 0.22 - 200
µS
Byte Load Cycle Time-out TBLCO 300 - -
µS
Note: All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL.
