3 Interfaces
3.1 Introduction
The QT60xx0 can be configured to communicate either over
an I
2
C bus or a shift register type Serial Peripheral Interface
(SPI).
The pins A0, A1 are used to configure the type of interface
and the I
2
C address if this mode is used. The modes and I
2
C
addresses are available as shown in Table 3.1 below.
I
2
C Address 117VddVdd
I
2
C Address 17VssVdd
I
2
C Address 7VddVss
Shift RegisterVssVss
InterfaceA0A1
Table 3.1 Interface Details
3.2 Shift Register Output Mode
When the option jumpers are both set at Vss, the device
disables the I
2
C interface and instead generates output
suitable for driving a shift register.
The shift register data is output at pin 27 (SDA). The clock is
output at pin 28 (SCL). The data is clocked on the
positive-going transition of SCL. Data is transferred from the
shift registers to the latched outputs on the positive-going
transition of LATCH. An example shift register connection is
shown in Figure 3.1.
The shift register data is output over the duration of a matrix
scan, as each key is being processed, and it is latched at the
end of the scan. The overall communication time depends on
the matrix scan time.
75us mint
SDA
-
SCL
SDA data to SCL clock hold time
500ns mint
LATCH
LATCH pulse width
125us mint
SCH
SCL high pulse width
500ns mint
SCL
SCL low pulse width
UnitsLegendParameter
Table 3.2 Shift Register
Figure 3.2, page 11 shows a full shift register cycle with keys
3, 10 and 15 activated. Key Scan represents the time when
the chip is measuring signal from each key. SCL, SDA and
LATCH represent their respective signals from the chip. SCL
is an active low clock output. SDA is the data output; high if
the key is in detect and low if it is not. LATCH pulses low
when the data transfer is complete.
Data output proceeds as soon as the key has been
processed. Most keys do not get processed during the key
scan. If so, these keys are processed and the data is output
after the complete key scan.
The internal settings of the device in Shift Register mode are
the default factory settings found in Table 6.2. This means the
device will operate with a Burst Length of 48 on all keys, and
a Sleep time of 125ms for example. These settings cannot be
changed in this mode.
In Shift Register mode, the CHANGE pin is inactive and
should be left open.
3.3 I
2
C Port
These devices use I
2
C communications, in slave mode only.
The QT60160/QT60240 will only respond to the correct
address match. I
2
C operating parameters are as follows:
Max Data Transfer: 100KHz
Address: 7-bit
The match address is selected via pins A0 and A1. Table 3.1
shows the address selections.
The QT60160/QT60240 allows multiple byte transmissions to
provide a more efficient communication. This is particularly
useful to retrieve several information bytes at once. Every
time the host retrieves data from the QT60160/QT60240, an
internal address pointer is incremented.
Therefore, the host only needs to write the initial address
pointer of interest (the lowest address), followed by read
cycles for as many bytes as required.
lQ
10 QT60240-ISG R8.06/0906
Figure 3.1 Shift Register Output
Q0
Q2
Q3
Q4
Q5
Q6
Q7
DS
SH_CP
ST_CP
/Q7
74HC595
Outputs, keys 16 to 23
Q0
Q2
Q3
Q4
Q5
Q6
Q7
DS
SH_CP
ST_CP
/Q7
74HC595
Outputs, keys 8 to 15
Q0
Q2
Q3
Q4
Q5
Q6
Q7
DS
SH_CP
ST_CP
/Q7
74HC595
Outputs, keys 0 to 7
QT60160/60240
SDA
SCL
Latch
27
28
9
