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QL4016-1PF100M

QL4016-1PF100M首页预览图
型号: QL4016-1PF100M
PDF文件:
  • QL4016-1PF100M PDF文件
  • QL4016-1PF100M PDF在线浏览
功能描述: 16,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM
PDF文件大小: 478.65 Kbytes
PDF页数: 共18页
制造商: ETC[List of Unclassifed Manufacturers]
制造商LOGO: ETC[List of Unclassifed Manufacturers] LOGO
制造商网址:
捡单宝QL4016-1PF100M
PDF页面索引
120%
© 2002 QuickLogic Corp ora ti on
www.quicklogic.com
3
QL4016 Quic kRAM Data Sheet Rev I
Product Summary
Total of 118 I/O Pins
110 bi-directional input/output pins, PCI-compliant for 5.0 V and 3.3 V buses for
-1/-2/-3/-4 speed grades
8 high-drive input/distributed network pins
Eight Low-Skew Distributed Networks
Two array clock/control networks available to the logic cell flip-flop clock, set and reset
inputs—each driven by an input-only pin
Six global clock/control networks available to the logic cell F1, clock, set and reset inputs
and the input and I/O register clock, reset and enable inputs as well as the output enable
contro—each driven by an input-only or I/O pin, or any logic cell output or I/O cell
feedback
High Performance Silicon
Input + logic cell + output total delays = under 6 ns
Data path speeds over 400 MHz
Counter speeds over 300 MHz
FIFO speeds over 160+ MHz
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