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QL4016-1PF100M

QL4016-1PF100M首页预览图
型号: QL4016-1PF100M
PDF文件:
  • QL4016-1PF100M PDF文件
  • QL4016-1PF100M PDF在线浏览
功能描述: 16,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM
PDF文件大小: 478.65 Kbytes
PDF页数: 共18页
制造商: ETC[List of Unclassifed Manufacturers]
制造商LOGO: ETC[List of Unclassifed Manufacturers] LOGO
制造商网址:
捡单宝QL4016-1PF100M
PDF页面索引
120%
18
www.quicklogic.com
© 2002 QuickLogic Corporation
QL4016 QuickRAM Data Sheet Rev I
Contact Information
Telephone:408 990 4000 (US)
416 497 8884 (Canada)
44 1932 57 9011 (Europe)
49 89 930 86 170 (Germany)
852 8106 9091 (Asia)
81 45 470 5525 (Japan)
E-mail: info@quicklogic.com
Support:support@quicklogic.com
Web site:http://www.quicklogic.com/
Revision History
Copyright Information
Copyright © 2002 QuickLogic Corporation. All Rights Reserved.
The information contained in this product brief, and the accompanying software programs are pro-
tected by copyright. All rights are reserved by QuickLogic Corporation. QuickLogic Corporation
reserves the right to make periodic modifications of this product without obligation to notify any per-
son or entity of such revision. Copying, duplicating, selling, or otherwise distributing any part of this
product without the prior written consent of an authorized representative of QuickLogic is prohib-
ited.
QuickLogic, pASIC, and ViaLink are registered trademarks, and SpDE and QuickWorks are trade-
marks of QuickLogic Corporation.
Verilog is a registered trademark of Cadence Design Systems, Inc.
Table 15: Revision History
Revision Date Comments
A not avail. First release.
B not avail.
C not avail.
D not avail.
E not avail.
F not avail.
G not avail.
H May 2000 Update of AC/DC Specs and reformat
I May 2002
Added Kfactor, Power-up, JTAG and mechanical
drawing information. Reformatted.
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