QL16x24B
pASIC
®
1 Family
Very-High-Speed CMOS FPGA
4-21
Very High Speed
– ViaLink
metal-to-metal programmable–via
antifuse technology, allows counter speeds over 150 MHz and logic
cell delays of under 2 ns.
High Usable Density
– A 16-by-24 array of 384 logic cells
provides 4,000 usable ASIC gates (7,000 PLD gates) in 84-pin
PLCC, 100-pin and 144-pin TQFP, 144-pin CPGA and 160-pin
CQFP packages.
Low-Power, High-Output Drive
– Standby current typically 2 mA.
A 16-bit counter operating at 100 MHz consumes less than 50 mA.
Minimum IOL of 12 mA and IOH of 8 mA
Low-Cost, Easy-to-Use Design Tools
– Designs entered and
simulated using QuickLogic's new QuickWorks
development
environment, or with third-party CAE tools including Viewlogic,
Synopsys, Mentor, Cadence and Veribest. Fast, fully automatic place
and route on PC and workstation platforms using QuickLogic
software.
=
Up to 114 prog. I/O cells, 6 Input high-drive cells, 2 Input/Clk (high-drive) cells
pASIC 1
4
pASIC
HIGHLIGHTS
QL16x24B
Block Diagram
Rev C
…4,000
usable ASIC gates,
122 I/O pins
384 Logic Cells
