Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 97
Register Descriptions
This register enables various errors to generate an SMI HI special cycle. When an error flag is set
in the FERR or NERR registers, it can generate an SMI HI special cycle when enabled in the
SMICMD register. Note that one and only one message type can be enabled.
3.6.33 BUF_SERRCMD – Memory Buffer SERR Command Register
(D0:F1)
Address Offset: 7Ch
Access: R/W
Size: 8 bits
Default Value: 00h
This register enables various errors to generate an SERR HI special cycle. When an error flag is set
in the FERR or NERR registers, it can generate an SERR HI special cycle when enabled in the
SERRCMD register. Note that only one message type can be enabled.
Bit Field
Default &
Access
Description
7:4 0h Reserved
3 0b
R/W
Internal DRAM Interface to PMWB Parity Error SMI Enable. Controls whether or
not an SMI is generated when bit 3 of the BUF_FERR or BUF_NERR register is set.
0 = No SMI on internal DRAM interface to PMWB parity error detection
1 = Enable SMI generation on internal DRAM interface to PMWB parity error
detection
2 0b
R/W
Internal System Bus or I/O to PMWB Parity Error SMI Enable. Controls whether
or not an SMI is generated when bit 2 of the BUF_FERR or BUF_NERR register is
set.
0 = No SMI on internal System Bus or I/O to PMWB parity error detection
1 = Enable SMI generation on internal System Bus or I/O to PMWB data parity error
detection
1 0b
R/W
Internal PMWB to System Bus Parity Error SMI Enable. Controls whether or not
an SMI is generated when bit 1 of the BUF_FERR or BUF_NERR register is set.
0 = No SMI on internal PMWB to System Bus parity error detection
1 = Enable SMI generation on internal PMWB to System Bus parity error detection
0 0b
R/W
Internal PMWB to DRAM Interface Parity Error SMI Enable. Controls whether or
not an SMI is generated when bit 0 of the BUF_FERR or BUF_NERR register is set.
0 = No SMI on internal PMWB to DRAM interface parity error detection
1 = Enable SMI generation on internal PMWB to DRAM interface parity error
detection
Bit Field
Default &
Access
Description
7:4 0h Reserved
3 0b
R/W
Internal DRAM Interface to PMWB Parity Error SERR Enable. Controls
whether or not an SERR is generated when bit 3 of the BUF_FERR or
BUF_NERR register is set.
0 = No SERR on internal DRAM interface to PMWB parity error detection
1 = Enable SERR generation on internal DRAM interface to PMWB parity error
detection
