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QGE7520MC-SL8EE

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型号: QGE7520MC-SL8EE
PDF文件:
  • QGE7520MC-SL8EE PDF文件
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功能描述: Intel® E7520 Memory Controller Hub (MCH)
PDF文件大小: 2594.09 Kbytes
PDF页数: 共282页
制造商: INTEL[Intel Corporation]
制造商LOGO: INTEL[Intel Corporation] LOGO
制造商网址: http://www.intel.com
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120%
96 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
3.6.31 BUF_SCICMD – Memory Buffer SCI Command Register
(D0:F1)
Address Offset: 78h
Access: R/W
Size: 8 bits
Default Value: 00h
This register enables various errors to generate an SCI Hub Interface (HI) special cycle. When an
error flag is set in the FERR or NERR registers, it can generate an SCI HI special cycle when
enabled in the SCICMD registers. Note that only one message type can be enabled.
3.6.32 BUF_SMICMD – Memory Buffer SMI Command Register
(D0:F1)
Address Offset: 7Ah
Access: R/W
Size: 8 bits
Default Value: 00h
1 0b
R/W
Internal PMWB to System Bus Parity Error Mask. This bit is sticky through
reset.
0 = Enable Internal PMWB to System Bus Parity Error detection and reporting
1 = Mask Internal PMWB to System Bus Parity Error detection and reporting
0 0b
R/W
Internal PMWB to DRAM Parity Error Mask. This bit is sticky through reset.
0 = Enable Internal PMWB to DRAM Parity Error detection and reporting
1 = Mask Internal PMWB to DRAM Parity Error detection and reporting
Bit Field
Default &
Access
Description
Bit Field
Default &
Access
Description
7:4 0h Reserved
3 0b
R/W
Internal DRAM Interface to PMWB Parity Error SCI Enable. Controls whether or
not an SCI is generated when bit 3 of the BUF_FERR or BUF_NERR register is set.
0 = No SCI on internal DRAM interface to PMWB parity error detection
1 = Enable SCI generation on internal DRAM interface to PMWB parity error
detection
2 0b
R/W
Internal System Bus or I/O to PMWB Parity Error SCI Enable. Controls whether
or not an SCI is generated when bit 2 of the BUF_FERR or BUF_NERR register is
set.
0 = No SCI on internal System Bus or I/O to PMWB parity error detection
1 = Enable SCI generation on internal System Bus or I/O to PMWB data parity error
detection
1 0b
R/W
Internal PMWB to System Bus Parity Error SCI Enable. Controls whether or not
an SCI is generated when bit 0 of the BUF_FERR or BUF_NERR register is set.
0 = No SCI on internal PMWB to System Bus parity error detection
1 = Enable SCI generation on internal PMWB to System Bus parity error detection
0 0b
R/W
Internal PMWB to DRAM Interface Parity Error SCI Enable. Controls whether or
not an SCI is generated when bit 1 of the BUF_FERR or BUF_NERR register is set.
0 = No SCI on internal PMWB to DRAM interface parity error detection
1 = Enable SCI generation on internal PMWB to DRAM interface parity error
detection
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