Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 95
Register Descriptions
3.6.30 BUF_ERRMASK – Memory Buffer Error Mask Register
(D0:F1)
Address Offset: 74h
Access: R/W
Size: 8 bits
Default Value: 00h
This register masks PMWB errors from being recognized, preventing them from being logged at
the unit or global level, and no interrupt messages are generated. These bits are sticky through
reset.
Bit Field
Default &
Access
Description
7:4 0h Reserved
3 0b
R/WC
Internal DRAM to PMWB Parity Error Detected. Error detected when a cache
line read from DRAM was written to the PMWB as part of a Read/Modify/Write
operation (partial write). This bit is sticky through reset. System software clears
this bit by writing a 1 to the location.
0 = No internal DRAM interface to PMWB parity error detected
1 = Internal DRAM interface to PMWB parity error detected. Non fatal
2 0b
R/WC
Internal System Bus or I/O to PMWB Parity Error Detected. Error detected on
a System Bus or I/O write of a line to the PMWB. This bit is sticky through reset.
System software clears this bit by writing a 1 to the location.
0 = No internal data parity error detected on line write
1 = Internal data parity error detected on line write to PMWB. Non fatal
1 0b
R/WC
Internal PMWB to System Bus Parity Error Detected. This bit is sticky through
reset. System software clears this bit by writing a 1 to the location.
0 = No internal PMWB to System Bus parity error detected
1 = Internal PMWB to System Bus parity error detected. Non-fatal
0 0b
R/WC
Internal PMWB to DRAM Parity Error Detected. Error detected when PMWB is
flushed to DRAM. This bit is sticky through reset. System software clears this bit
by writing a 1 to the location.
0 = No internal PMWB to DRAM interface parity error detected
1 = Internal PMWB to DRAM interface parity error detected. Non-fatal
Bit Field
Default &
Access
Description
7:4 00h Reserved
3 0b
R/W
Internal DRAM to PMWB Parity Error Mask. This bit is sticky through reset.
0 = Enable Internal DRAM to PMWB Parity Error detection and reporting
1 = Mask Internal DRAM to PMWB Parity Error detection and reporting
2 0b
R/W
Internal System Bus or I/O to PMWB Parity Error Mask. This bit is sticky
through reset.
0 = Enable internal System Bus or I/O to PMWB Parity Error detection and
reporting
1 = Mask internal System Bus or I/O to PMWB Parity Error detection and
reporting