94 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
3.6.28 BUF_FERR – Memory Buffer First Error Register (D0:F1)
Address Offset: 70h
Access: R/WC
Size: 8 bits
Default Value: 00h
This register stores the first error related to the coherent Posted Memory Write Buffer (PMWB).
Only one error bit will be set in this register. Any future errors (NEXT errors) will be set in the
BUF_NERR register. No further error bits in the BUF_FERR register will be set until the existing
error bit is cleared. These bits are sticky through reset. Software clears these bits by writing a 1 to
the bit location.
Note: If multiple errors are reported in the same clock as the first error, all errors are latched.
3.6.29 BUF_NERR – Memory Buffer Next Error Register (D0:F1)
Address Offset: 72h
Access: R/W
Size: 8 bits
Default Value: 00h
This register stores all errors after the first error related to the coherent Posted Memory Write
Buffer (PMWB). These bits are sticky through reset. Software clears these bits by writing a 1 to the
bit location.
Bit Field
Default &
Access
Description
7:4 0h Reserved
3 0b
R/WC
Internal DRAM to PMWB Parity Error Detected. Error detected when a cache
line read from DRAM was written to the PMWB as part of a Read/Modify/Write
operation (partial write). This bit is sticky through reset. System software clears
this bit by writing a 1 to the location.
0 = No internal DRAM interface to PMWB parity error detected
1 = Internal DRAM interface to PMWB parity error detected. Non fatal
2 0b
R/WC
Internal System Bus or I/O to PMWB Parity Error Detected. Error detected on
a System Bus or I/O write of a line to the PMWB. This bit is sticky through reset.
System software clears this bit by writing a 1 to the location.
0 = No internal data parity error detected on line write
1 = Internal data parity error detected on line write to PMWB. Non fatal
1 0b
R/WC
Internal PMWB to System Bus Parity Error Detected. This bit is sticky through
reset. System software clears this bit by writing a 1 to the location.
0 = No internal PMWB to System Bus parity error detected
1 = Internal PMWB to System Bus parity error detected. Non-fatal
0 0b
R/WC
Internal PMWB to DRAM Parity Error Detected. Error detected when PMWB is
flushed to DRAM. This bit is sticky through reset. System software clears this bit
by writing a 1 to the location.
0 = No internal PMWB to DRAM interface parity error detected
1 = Internal PMWB to DRAM interface parity error detected. Non-fatal
