92 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
3.6.27 SYSBUS_MCERRCMD – System Bus MCERR# Command
Register (D0:F1)
Address Offset: 6E – 6Fh
Access R/W
Size 16 Bits
Default 0000h
This register enables various errors to assert the MCERR# signal on the system bus. When an error
flag is set in the SYSBUS_FERR or SYSBUS_NERR register, it can generate a MCERR# when
enabled in the MCERRCMD.
8 0b
R/W
Parity error from memory SERR Enable. Controls whether or not an SERR is
generated when bit 8 of the SYSBUS_FERR or SYSBUS_NERR is set.
0 = No SERR generated on parity error detection.
1 = Enable SERR generation on parity error detection.
7 0b
R/W
System Bus BINIT# detected SERR Enable. Controls whether or not an SERR is
generated when bit 7 of the SYSBUS_FERR or SYSBUS_NERR register is set.
0 = No SERR generated on System Bus BINIT# detection
1 = Enable SERR generation on System Bus BINIT# detection
6 0b
R/W
System Bus MCERR# detected SERR Enable. Controls whether or not an SERR
is generated when bit 6 of the SYSBUS_FERR or SYSBUS_NERR register is set.
0 = No SERR generated on System Bus MCERR# detection
1 = Enable SERR generation on System Bus MCERR# detection
5 0b
R/W
Non-DRAM Lock Error SERR Enable. Controls whether or not an SERR is
generated when bit 5 of the SYSBUS_FERR or SYSBUS_NERR register is set.
0 = No SERR generated on Non-DRAM Lock Error detection
1 = Enable SERR generation on Non-DRAM Lock Error detection
4 0b
R/W
System Bus Address Above TOM SERR Enable. Controls whether or not an
SERR is generated when bit 4 of the SYSBUS_FERR or SYSBUS_NERR register is
set.
0 = No SERR generated on System Bus address above TOM detection
1 = Enable SERR generation on System Bus address above TOM detection
3 0b
R/W
System Bus Data Parity Error SERR Enable. Controls whether or not an SERR is
generated when bit 3 of the SYSBUS_FERR or SYSBUS_NERRR register is set.
0 = No SERR generated on System Bus Data Parity Error detection
1 = Enable SERR generation on System Bus Data Parity Error detection
2 0b
R/W
System Bus Address Strobe Glitch Detected SERR Enable. Controls whether or
not an SERR is generated when bit 2 of the SYSBUS_FERR or SYSBUS_NERR
register is set.
0 = No SERR generated on System Bus address strobe glitch detection
1 = Enable SERR generation on System Bus address strobe glitch detection
1 0b
R/W
System Bus Data Strobe Glitch Detected SERR Enable. Controls whether or not
an SERR is generated when bit 1 of the SYSBUS_FERR or SYSBUS_NERR
register is set.
0 = No SERR generated on System Bus data strobe glitch detection
1 = Enable SERR generation on System Bus data strobe glitch detection
0 0b
R/W
System Bus Request/Address Parity Error Detected SERR Enable. Controls
whether or not an SERR is generated when bit 0 of the SYSBUS_FERR or
SYSBUS_NERR register is set.
0 = No SERR generated on System Bus request/address parity error detection
1 = Enable SERR generation on System Bus request/address detection
Bit Field
Default &
Access
Description