Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 91
Register Descriptions
3.6.26 SYSBUS_SERRCMD – System Bus SERR Command
Register (D0:F1)
Address Offset: 6C – 6Dh
Access R/W
Size 16 Bits
Default 0000h
This register enables various errors to generate an SERR HI special cycle. When an error flag is set
in the SYSBUS_FERR or SYSBUS_NERR register, it can generate an SERR HI special cycle
when enabled in the SERRCMD register. Note that one and only one message type can be enabled.
5 0b
R/W
Non-DRAM Lock Error SMI Enable. Controls whether or not an SMI is
generated when bit 5 of the SYSBUS_FERR or SYSBUS_NERR register is set.
0 = No SMI generated on Non-DRAM Lock Error detection
1 = Enable SMI generation on Non-DRAM Lock Error detection
4 0b
R/W
System Bus Address Above TOM SMI Enable. Controls whether or not an SMI
is generated when bit 4 of the SYSBUS_FERR or SYSBUS_NERR register is
set.
0 = No SMI generated on System Bus address above TOM detection
1 = Enable SMI generation on System Bus address above TOM detection
3 0b
R/W
System Bus Data Parity Error SMI Enable. Controls whether or not an SMI is
generated when bit 3 of the SYSBUS_FERR or SYSBUS_NERRR register is set.
0 = No SMI generated on System Bus Data Parity Error detection
1 = Enable SMI generation on System Bus Data Parity Error detection
2 0b
R/W
System Bus Address Strobe Glitch Detected SMI Enable. Controls whether or
not an SMI is generated when bit 2 of the SYSBUS_FERR or SYSBUS_NERR
register is set.
0 = No SMI generated on System Bus address strobe glitch detection
1 = Enable SMI generation on System Bus address strobe glitch detection
1 0b
R/W
System Bus Data Strobe Glitch Detected SMI Enable. Controls whether or not
an SMI is generated when bit 1 of the SYSBUS_FERR or SYSBUS_NERR
register is set.
0 = No SMI generated on System Bus data strobe glitch detection
1 = Enable SMI generation on System Bus data strobe glitch detection
0 0b
R/W
System Bus Request/Address Parity Error Detected SMI Enable. Controls
whether or not an SMI is generated when bit 0 of the SYSBUS_FERR or
SYSBUS_NERR register is set.
0 = No SMI generated on System Bus request/address parity error detection
1 = Enable SMI generation on System Bus request/address detection
Bit Field
Default &
Access
Description
Bit Field
Default &
Access
Description
15:10 00h Reserved
9 0b
R/W
Parity error from I/O subsystem SERR Enable. Controls whether or not an SERR is
generated when bit 9 of the SYSBUS_FERR or SYSBUS_NERR is set.
0 = No SERR generated on parity error detection.
1 = Enable SERR generation on parity error detection.