Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 9
4.1.6 PCI Express Enhanced Configuration Aperture ................................................205
4.1.7 I/O APIC Memory Space ...................................................................................205
4.1.8 System Bus Interrupt Memory Space................................................................206
4.1.9 High SMM Memory Space.................................................................................206
4.1.10 PCI Device Memory (MMIO) .............................................................................206
4.1.10.1 Device 2 Memory and Prefetchable Memory...................................207
4.1.10.2 Device 3 Memory and Prefetchable Memory...................................207
4.1.10.3 Device 4 Memory and Prefetchable Memory...................................208
4.1.10.4 Device 5 Memory and Prefetchable Memory...................................208
4.1.10.5 Device 6 Memory and Prefetchable Memory...................................208
4.1.10.6 Device 7 Memory and Prefetchable Memory...................................208
4.1.10.7 HI Subtractive Decode .....................................................................209
4.2 I/O Address Space...........................................................................................................209
4.3 System Management Mode (SMM) Space ......................................................................209
4.3.1 SMM Addressing Ranges..................................................................................210
4.3.1.1 SMM Space Restrictions..................................................................210
4.3.1.2 SMM Space Definition......................................................................210
4.4 Memory Reclaim Background..........................................................................................211
4.4.1 Memory Remapping ..........................................................................................211
5 Functional Description....................................................................................................213
5.1 Internal Feature Set .........................................................................................................213
5.1.1 Coherent Memory Write Buffer..........................................................................213
5.1.2 Internal Data Protection.....................................................................................213
5.2 Integrated DMA Controller ...............................................................................................213
5.3 Front Side Bus (FSB).......................................................................................................214
5.3.1 In-Order Queue (IOQ) .......................................................................................214
5.3.2 System Bus Interrupts .......................................................................................214
5.3.3 System Bus Dynamic Inversion.........................................................................214
5.3.4 Front Side Bus Parity.........................................................................................215
5.4 Memory Interface .............................................................................................................216
5.4.1 Memory Interface Performance Optimizations ..................................................217
5.4.1.1 DDR Overlapped Command Scheduling .........................................217
5.4.1.2 Aggressive Page-Closed Policy with Look-Ahead ...........................217
5.4.1.3 Symmetric Addressing Mode ...........................................................217
5.4.2 Memory Interface RASUM ................................................................................217
5.4.2.1 DRAM ECC – Intel
®
x4 Single Device Data Correction
(x4 SDDC)........................................................................................217
5.4.2.2 Integrated Memory Scrub Engine ....................................................218
5.4.2.3 Retry on Uncorrectable Error ...........................................................218
5.4.2.4 Integrated Memory Initialization Engine...........................................218
5.4.2.5 DIMM Sparing Function ...................................................................219
5.4.2.6 DIMM Error Rate Threshold Counters .............................................220
5.4.2.7 Memory Mirroring.............................................................................221
5.4.3 Memory Address Translation Tables.................................................................223
5.4.4 Quad Word Ordering .........................................................................................227
5.4.5 DDR Clock Voltage Crossing (VOX) Calibration ...............................................227
5.4.6 Thermal Management .......................................................................................228
5.4.6.1 Thermal Management Algorithmic Description ................................228
5.4.6.2 Thermal Management Threshold Calculation ..................................229
5.5 PCI Express Interface......................................................................................................230
5.5.1 PCI Express Training.........................................................................................231
5.5.2 PCI Express Retry .............................................................................................231
5.5.3 PCI Express Link Recovery...............................................................................231
5.5.4 PCI Express Data Protection.............................................................................231
5.5.5 PCI Express Retrain..........................................................................................232