Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 87
Register Descriptions
Bit Field
Default &
Access
Description
15:10 00h Reserved
9 0b
R/WC
Parity error from I/O subsystem. This bit is sticky through reset. System software
clears this bit by writing a ‘1’ to the location.
0 = No parity error detected.
1 = Parity error detected on data from I/O subsystem heading for FSB. Non-fatal
8 0b
R/WC
Parity error from memory. This bit is sticky through reset. System software clears
this bit by writing a ‘1’ to the location.
0 = No parity error detected.
1 = Parity error detected on data from memory heading for FSB. Non-fatal
7 0b
R/WC
System Bus BINIT# detected. This bit is sticky through reset. System software
clears this bit by writing a ‘1’ to the location.
0 = No system bus BINIT# detected
1 = This bit is set on an electrical high-to-low transition (0 to 1) of BINIT#. Fatal
6 0b
R/WC
System Bus MCERR# detected. This bit is sticky through reset. System
software clears this bit by writing a ‘1’ to the location.
0 = No system bus MCERR# detected
1 = This bit is set on an electrical high-to-low transition (0 to 1) of MCERR#
when the MCH is not driving. Non-fatal
5 0b
R/WC
Non-DRAM Lock Error (NDLOCK). This bit is sticky through reset. System
software clears this bit by writing a ‘1’ to the location.
0 = No DRAM Lock Error detected
1 = MCH detected a lock operation to memory space that did not map into
DRAM. Non-fatal
4 0b
R/WC
System Bus Address Above TOM (SBATOM). This bit is sticky through reset.
System software clears this bit by writing a ‘1’ to the location.
0 = No system bus address above TOM detected
1 = MCH has detected an address above DRB[7], which is the Top of Memory
and above 4 GB. If the system has less than 4 GB of DRAM, then addresses
between DRB[7] and 4 GB are sent to HI. Non-fatal
3 0b
R/WC
System Bus Data Parity Error (SBDPAR). This bit is sticky through reset.
System software clears this bit by writing a ‘1’ to the location.
0 = No system bus parity error detected.
1 = MCH has detected a data parity error on the system bus. Non-fatal
2 0b
R/WC
System Bus Address Strobe Glitch Detected (SBAGL). This bit is sticky
through reset. System software clears this bit by writing a ‘1’ to the location.
0 = No system bus address strobe glitch detected.
1 = MCH has detected a glitch one of the System Bus address strobes. Fatal
1 0b
R/WC
System Bus Data Strobe Glitch Detected (SBDGL). This bit is sticky through
reset. System software clears this bit by writing a ‘1’ to the location.
0 = No system bus data strobe glitch detected.
1 = MCH has detected a glitch one of the System Bus data strobes. Fatal
0 0b
R/WC
System Bus Request/Address Parity Error Detected (SBRPR). This bit is
sticky through reset. System software clears this bit by writing a ‘1’ to the location.
0 = No system bus request/address parity error detected.
1 = MCH has detected a parity error on either the address or request signals of
the System Bus. Fatal