86 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
This register enables various errors to assert the MCERR# signal on the system bus. When an error
flag is set in the FERR or NERR registers, it can generate a MCERR# when enabled in the
MCERRCMD.
3.6.21 SYSBUS_FERR – System Bus First Error Register (D0:F1)
Address Offset: 60 – 61h
Access R/WC
Size 16 Bits
Default 0000h
This register stores the first error related to the system bus. Only one error bit will be set in this
register. Any future errors (NEXT errors) will be net in the SYSBUS_NERR register. No further
error bits in the SYSBUS_FERR register will be set until the existing error bit is cleared. These bits
are sticky through reset. Software clears these bits by writing a ‘1’ to the bit location.
Note: If multiple errors are reported in the same clock as the first error, all errors are latched.
Bit Field
Default &
Access
Description
7 0b Reserved
6 0b
R/W
Hub Interface Target Abort MCERR# Enable. Controls whether or not an
MCERR# is generated when bit 6 of either the HI_FERR or HI_NERR register is
set.
0 = No MCERR# generated on HI Target Abort detection
1 = Enable MCERR# generation on HI Target Abort detection
5 0b
R/W
Enhanced Configuration Access Error MCERR# Enable. Controls whether or
not an MCERR# is generated when bit 5 of either the HI_FERR or HI_NERR
register is set.
0 = No MCERR# generated on HI Enhanced Config Access error detection.
1 = Enable MCERR# generation on HI Enhanced Config Access error detection
4 0b
R/W
HI Data Parity Error MCERR# Enable. Controls whether or not an MCERR is
generated when bit 4 of either the HI_FERR or HI_NERR register is set.
0 = No MCERR# generated on HI Data Parity error detection
1 = Enable MCERR# generation on HI Data Parity error detection
3 0b
R/W
Out of Range Address Error MCERR# Enable. Controls whether or not an
MCERR# is generated when bit 3 of either the HI_FERR or HI_NERR register is
set.
0 = No MCERR# generated on HI Out of Range Address error detection
1 = Enable MCERR# generation on HI Out of Range Address error detection
2 0b
R/W
HI Internal Parity Error MCERR# Enable. Controls whether or not an MCERR#
is generated when bit 2 of either the HI_FERR or HI_NERR register is set.
0 = No MCERR# generated on HI Internal Parity error detection
1 = Enable MCERR# generation on HI Internal Parity error detection
1 0b
R/W
Illegal Access from HI MCERR# Enable. Controls whether or not an MCERR#
is generated when bit 1 of either the HI_FERR or HI_NERR register is set.
0 = No MCERR# generated on HI Illegal Access error detection
1 = Enable MCERR# generation on HI Illegal Access error detection
0 0b
R/W
HI Address/Command Parity Error MCERR# Enable. Controls whether or not
an MCERR# is generated when bit 0 of either the HI_FERR or HI_NERR register
is set.
0 = No MCERR# generated on HI Address/Command Parity error detection
1 = Enable MCERR# generation on HI Address/Command Parity error detection
