Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 85
Register Descriptions
3.6.19 HI_SERRCMD – Hub Interface SERR Command Register
(D0:F1)
Address Offset: 5Ch
Access R/W
Size 8 Bits
Default 00h
This register enables various errors to generate an SERR HI special cycle. When an error flag is set
in the FERR or NERR registers, it can generate an SERR HI special cycle when enabled in the
SERRCMD register. Note that one and only one message type can be enabled.
3.6.20 HI_MCERRCMD – Hub Interface MCERR# Register (D0:F1)
Address Offset: 5Eh
Access R/W
Size 8 Bits
Default 00h
Bit Field
Default &
Access
Description
7 0b Reserved
6 0b
R/W
Hub Interface Target Abort SERR Enable. Controls whether or not an SERR is
generated when bit 6 of either the HI_FERR or HI_NERR register is set.
0 = No SERR generated on HI Target Abort detection
1 = Enable SERR generation on HI Target Abort detection
5 0b
R/W
Enhanced Configuration Access Error SERR Enable. Controls whether or not
an SERR is generated when bit 5 of either the HI_FERR or HI_NERR register is
set.
0 = No SERR generated on HI Enhanced Config Access error detection.
1 = Enable SERR generation on HI Enhanced Config Access error detection
4 0b
R/W
HI Data Parity Error SERR Enable. Controls whether or not an SERR is
generated when bit 4 of either the HI_FERR or HI_NERR register is set.
0 = No SERR generated on HI Data Parity error detection
1 = Enable SERR generation on HI Data Parity error detection
3 0b
R/W
Out of Range Address Error SERR Enable. Controls whether or not an SERR
is generated when bit 3 of either the HI_FERR or HI_NERR register is set.
0 = No SERR generated on HI Out of Range Address error detection
1 = Enable SERR generation on HI Out of Range Address error detection
2 0b
R/W
HI Internal Parity Error SERR Enable. Controls whether or not an SERR is
generated when bit 2 of either the HI_FERR or HI_NERR register is set.
0 = No SERR generated on HI Internal Parity error detection
1 = Enable SERR generation on HI Internal Parity error detection
1 0b
R/W
Illegal Access from HI SERR Enable. Controls whether or not an SERR is
generated when bit 1 of either the HI_FERR or HI_NERR register is set.
0 = No SERR generated on HI Illegal Access error detection
1 = Enable SERR generation on HI Illegal Access error detection
0 0b
R/W
HI Address/Command Parity Error SERR Enable. Controls whether or not an
SERR is generated when bit 0 of either the HI_FERR or HI_NERR register is set.
0 = No SERR generated on HI Address/Command Parity error detection
1 = Enable SERR generation on HI Address/Command Parity error detection
