84 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
3.6.18 HI_SMICMD – Hub Interface SMI Command Register (D0:F1)
Address Offset: 5Ah
Access R/W
Size 8 Bits
Default 00h
This register enables various errors to generate an SMI HI special cycle. When an error flag is set
in the FERR or NERR registers, it can generate an SMI HI special cycle when enabled in the
SMICMD register. Note that one and only one message type can be enabled.
1 0b
R/W
Illegal Access from HI SCI Enable. Controls whether or not an SCI is generated
when bit 1 of either the HI_FERR or HI_NERR register is set.
0 = No SCI generated on HI Illegal Access error detection
1 = Enable SCI generation on HI Illegal Access error detection
0 0b
R/W
HI Address/Command Parity Error SCI Enable. Controls whether or not an SCI
is generated when bit 0 of either the HI_FERR or HI_NERR register is set.
0 = No SCI generated on HI Address/Command Parity error detection
1 = Enable SCI generation on HI Address/Command Parity error detection
Bit Field
Default &
Access
Description
Bit Field
Default &
Access
Description
7 0b Reserved
6 0b
R/W
Hub Interface Target Abort SMI Enable. Controls whether or not an SMI is
generated when bit 6 of either the HI_FERR or HI_NERR register is set.
0 = No SMI generated on HI Target Abort detection
1 = Enable SMI generation on HI Target Abort detection
5 0b
R/W
Enhanced Configuration Access Error SMI Enable. Controls whether or not an
SMI is generated when bit 5 of either the HI_FERR or HI_NERR register is set.
0 = No SMI generated on HI Enhanced Config Access error detection.
1 = Enable SMI generation on HI Enhanced Config Access error detection
4 0b
R/W
HI Data Parity Error SMI Enable. Controls whether or not an SMI is generated
when bit 4 of either the HI_FERR or HI_NERR register is set.
0 = No SMI generated on HI Data Parity error detection
1 = Enable SMI generation on HI Data Parity error detection
3 0b
R/W
Out of Range Address Error SMI Enable. Controls whether or not an SMI is
generated when bit 3 of either the HI_FERR or HI_NERR register is set.
0 = No SMI generated on HI Out of Range Address error detection
1 = Enable SMI generation on HI Out of Range Address error detection
2 0b
R/W
HI Internal Parity Error SMI Enable. Controls whether or not an SMI is
generated when bit 2 of either the HI_FERR or HI_NERR register is set.
0 = No SMI generated on HI Internal Parity error detection
1 = Enable SMI generation on HI Internal Parity error detection
1 0b
R/W
Illegal Access from HI SMI Enable. Controls whether or not an SMI is generated
when bit 1 of either the HI_FERR or HI_NERR register is set.
0 = No SMI generated on HI Illegal Access error detection
1 = Enable SMI generation on HI Illegal Access error detection
0 0b
R/W
HI Address/Command Parity Error SMI Enable. Controls whether or not an
SMI is generated when bit 0 of either the HI_FERR or HI_NERR register is set.
0 = No SMI generated on HI Address/Command Parity error detection
1 = Enable SMI generation on HI Address/Command Parity error detection
