82 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
3.6.15 HI_NERR – Hub Interface Next Error Register (D0:F1)
Address Offset: 52h
Access R/WC
Size 8 Bits
Default 00h
As mentioned in Section 3.6.14, the first HI error will be stored in the HI_FERR register. This
register stores all subsequent HI errors. Multiple bits in this register may be set. The bit definitions
in this register are identical to those in Section 3.6.14, “HI_FERR – Hub Interface First Error
Register (D0:F1)” on page 3-81.
3.6.16 HI_ERRMASK – Hub Interface Error Mask Register (D0:F1)
Address Offset: 54h
Access R/W
Size 8 Bits
Default 00h
This register masks HI unit errors from being recognized, preventing them from being logged at the
unit or global level, and no interrupt/messages are generated. These bits are sticky through reset.
3 0b
R/WC
Out of Range Address Error Detected. This bit is sticky through reset. System
software clears this bit by writing a ‘1’ to the location.
0 = No Out of Range Address error detected.
1 = MCH has detected an attempted HI access to an Out of Range Address
(includes addresses above 4G sent to the HI). Fatal.
2 0b
R/WC
HI Internal Parity Error Detected. This bit is sticky through reset. System
software clears this bit by writing a ‘1’ to the location.
0 = No Internal Parity error detected.
1 = MCH HI bridge has detected an Internal Parity error. Non-fatal.
1 0b
R/WC
Illegal Access from HI Detected. This bit is sticky through reset. System
software clears this bit by writing a ‘1’ to the location.
0 = No Illegal Access error detected.
1 = MCH has detected an attempted illegal access from the HI. Fatal.
0 0b
R/WC
HI Address/Command Parity Error Detected. This bit is sticky through reset.
System software clears this bit by writing a ‘1’ to the location.
0 = No HI address or command parity error detected.
1 = MCH has detected a parity error on a HI address or command. Fatal.
Bit Field
Default &
Access
Description
Bit Field
Default &
Access
Description
7 0b Reserved
6 0b
R/W
Hub Interface Target Abort Mask. This bit is sticky through reset.
0 = Enable HI Target Abort detection and reporting
1 = Mask HI Target Abort detection and reporting
5 0b
R/W
Enhanced Configuration Access Error Mask. This bit is sticky through reset.
0 = Enable HI Enhanced Config Access error detection and reporting
1 = Mask HI Enhanced Config Access error detection and reporting
