Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 81
Register Descriptions
3.6.13 NERR_GLOBAL – Global Next Error Register (D0:F1)
Address Offset: 44 – 47h
Access R/WC
Size 32 Bits
Default 0000_0000h
The bit definitions are the same as defined for FERR_GLOBAL, and are sticky through reset.
3.6.14 HI_FERR – Hub Interface First Error Register (D0:F1)
Address Offset: 50h
Access R/WC
Size 8 Bits
Default 00h
This register stores the first error related to the Hub Interface. Only one error bit will be set in this
register. Any future errors (NEXT errors) will be net in the HI_NERR register. No further error bits
in the HI_FERR register will be set until the existing error bit is cleared. These bits are sticky
through reset. Software clears these bits by writing a ‘1’ to the bit location.
Note: If multiple errors are reported in the same clock as the first error, all errors are latched.
5 0b
R/WC
PCI Express* Port C Non-Fatal Error. This bit is sticky through reset. System
software clears this bit by writing a 1 to the location.
0 = No non-fatal PCI Express* Port C error.
1 = The MCH detected a non-fatal PCI Express* Port C error.
4 0b
R/WC
PCI Express* Port C1 Non-Fatal Error. This bit is sticky through reset. System
software clears this bit by writing a 1 to the location.
0 = No non-fatal PCI Express* Port C1 error.
1 = The MCH detected a non-fatal PCI Express* Port C1 error.
3:0 0h Reserved
Bit Field
Default &
Access
Description
Bit Field
Default &
Access
Description
7 0b Reserved
6 0b
R/WC
Hub Interface Target Abort. This bit is sticky through reset. System software
clears this bit by writing a ‘1’ to the location.
0 = No Target Abort on HI
1 = An MCH-initiated HI cycle terminated with a Target Abort. Non-fatal
5 0b
R/WC
Enhanced Configuration Access Error. This bit is sticky through reset. System
software clears this bit by writing a ‘1’ to the location.
0 = No Enhanced Configuration Access error
1 = A PCI Express Enhanced Configuration access was mistakenly targeting the
legacy interface. Fatal
4 0b
R/WC
HI Data Parity Error Detected. This bit is sticky through reset. System software
clears this bit by writing a ‘1’ to the location.
0 = No HI data parity error.
1 = MCH has detected a parity error on the data phase of a HI transaction.
Non-fatal.