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QGE7520MC-SL8EE

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型号: QGE7520MC-SL8EE
PDF文件:
  • QGE7520MC-SL8EE PDF文件
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功能描述: Intel® E7520 Memory Controller Hub (MCH)
PDF文件大小: 2594.09 Kbytes
PDF页数: 共282页
制造商: INTEL[Intel Corporation]
制造商LOGO: INTEL[Intel Corporation] LOGO
制造商网址: http://www.intel.com
捡单宝QGE7520MC-SL8EE
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120%
Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 79
Register Descriptions
3.6.12 FERR_GLOBAL – Global First Error Register (D0:F1)
Address Offset: 40 – 43h
Access R/WC
Size 32 Bits
Default 0000_0000h
This register is used to log various error conditions at the “unit” level. These bits are “sticky
through reset, and are set regardless of whether or not any error messages (SCI, SMI, SERR#,
MCERR#) are enabled and generated at the unit level. Specific error conditions within the various
functional units are logged in the unit-specific error registers that follow.
Errors are reported in the FERR/NERR registers indicating the detection of either a fatal or
non-fatal error. For these global error registers, a non-fatal error can be either an uncorrectable
error which is non-fatal, or a correctable error.
This register captures the FIRST global Fatal and the FIRST global Non-Fatal errors. For these
global error registers, a non-fatal error can be either an uncorrectable error which is non-fatal, or a
correctable error. Any future errors (NEXT errors) will be captured in the NERR_Global register.
No further error bits in this register will be set until the existing error bit is cleared.
Note: If multiple errors are reported in the same clock as the first error, all errors are latched.
Bit Field
Default &
Access
Description
31:28 000b Reserved
27 0b
R/WC
DRAM Controller Channel Fatal Error. This bit is sticky through reset. System
software clears this bit by writing a 1 to the location.
0 = No fatal DRAM I/F error.
1 = The MCH detected a fatal DRAM I/F error.
26 0b
R/WC
System Bus Fatal Error. This bit is sticky through reset. System software clears
this bit by writing a 1 to the location.
0 = No fatal system bus error.
1 = The MCH detected a fatal system bus error.
25 0b
R/WC
Hub Interface Fatal Error. This bit is sticky through reset. System software
clears this bit by writing a 1 to the location.
0 = No fatal HI error.
1 = The MCH detected a fatal HI error.
24 0b
R/WC
DMA Controller Fatal Error. This bit is sticky through reset. System software
clears this bit by writing a 1 to the location.
0 = No fatal DMA Controller error.
1 = The MCH detected a fatal DMA controller error.
23 0b
R/WC
PCI Express Port A Fatal Error. This bit is sticky through reset. System software
clears this bit by writing a 1 to the location.
0 = No fatal PCI Express Port A error.
1 = The MCH detected a fatal PCI Express Port A error.
22 0b
R/WC
PCI Express Port A1 Fatal Error. This bit is sticky through reset. System
software clears this bit by writing a 1 to the location.
0 = No fatal PCI Express Port A1 error.
1 = The MCH detected a fatal PCI Express Port A1 error.
21 0b
R/WC
PCI Express* Port B Fatal Error. This bit is sticky through reset. System
software clears this bit by writing a 1 to the location.
0 = No fatal PCI Express* Port B error.
1 = The MCH detected a fatal PCI Express* Port B error.
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