78 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
3.6.9 HDR – Header Type (D0:F1)
Address Offset: 0Eh
Access RO
Size 8 Bits
Default 00h
3.6.10 SVID – Subsystem Vendor Identification (D0:F1)
Address Offset: 2C – 2D
Access R/WO
Size 16 Bits
Default 0000h
The MCH treats the SVID and SID as a single 32 bit register with regard to R/WO functionality.
Any time a write access to the address 2C – 2Fh occurs, regardless of byte enables, entire 32 bit
register comprised of SVID and SID locks.
3.6.11 SID – Subsystem Identification (D0:F1)
Address Offset: 2E – 2F
Access R/WO
Size 16 Bits
Default 0000h
The MCH treats the SVID and SID as a single 32 bit register with regard to R/WO functionality.
Any time a write access to the address 2C – 2Fh occurs, regardless of byte enables, entire 32 bit
register comprised of SVID and SID locks.
Bit Field
Default &
Access
Description
7:0 00h Reserved
Bit Field
Default &
Access
Description
7:0 00h
RO
PCI Header (HDR). This value indicates the Header Type for MCH Device 0.
00h = MCH is a multi-function device with a standard header layout.
Bit Field
Default &
Access
Description
15:0 0000h
R/WO
Subsystem Vendor ID (SUBVID). This field should be programmed during
boot-up to indicate the vendor of the system board.
Bit Field
Default &
Access
Description
15:0 0000h
R/WO
Subsystem ID (SUBID). This field should be programmed during BIOS
initialization.