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QGE7520MC-SL8EE

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型号: QGE7520MC-SL8EE
PDF文件:
  • QGE7520MC-SL8EE PDF文件
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功能描述: Intel® E7520 Memory Controller Hub (MCH)
PDF文件大小: 2594.09 Kbytes
PDF页数: 共282页
制造商: INTEL[Intel Corporation]
制造商LOGO: INTEL[Intel Corporation] LOGO
制造商网址: http://www.intel.com
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120%
Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 77
Register Descriptions
3.6.5 RID – Revision Identification (D0:F1)
Address Offset: 08h
Access RO
Size 8 Bits
Default 09h
This register contains the revision number of MCH Device 0.
3.6.6 SUBC – Sub-Class Code (D0:F1)
Address Offset: 0Ah
Access RO
Size 8 Bits
Default 00h
3.6.7 BCC – Base Class Code (D0:F1)
Address Offset: 0Bh
Access RO
Size 8 Bits
Default FFh
3.6.8 MLT – Master Latency Timer (D0:F1)
Address Offset: 0Dh
Access RO
Size 8 Bits
Default 00h
Device 0 in the MCH is not a PCI master, therefore this register is not implemented.
Bit Field
Default &
Access
Description
7:0 09h
RO
Revision Identification Number (RID). This value indicates the revision
identification number for MCH Device 0. This number should always be the same
as the RID for Function 0.
09h = C1 stepping.
0Ah = C2 stepping.
0Ch = C4 stepping.
Bit Field
Default &
Access
Description
7:0 00h
RO
Sub-Class Code (SUBC). This value indicates the Sub Class Code into which
MCH Device 0 Function 1 falls.
00h = Bridge
Bit Field
Default &
Access
Description
7:0 FFh
RO
Base Class Code (BASEC). This value indicates the Base Class Code for MCH
Device 0, Function 1.
FFh = A 'non-defined' device. Since this function is used for error conditions, it
does not fall into any other class.
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