76 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
3.6.3 PCICMD – PCI Command Register (D0:F1)
Address Offset: 04 – 05h
Access: R/W
Size: 16 Bits
Default: 0000h
Since MCH Device 0 does not physically reside on PCI_A many of the bits are not implemented.
3.6.4 PCISTS – PCI Status Register (D0:F1)
Address Offset: 06 – 07h
Access R/WC
Size 16 Bits
Default 0000h
PCISTS is a 16-bit status register that reports the occurrence of error events on Device 0’s PCI
interface. Since MCH Device 0 does not physically reside on PCI_A many of the bits are not
implemented.
Bit Field
Default &
Access
Description
15:9 00h Reserved
8 0b
R/W
SERR Enable (SERRE). This is a global enable bit for Device 0 SERR
messaging. The MCH does not have an SERR signal. The MCH communicates
the SERR condition by sending an SERR message over the HI to the ICH.
0 = Disable. The SERR message is not generated by the MCH for Device 0.
1 = Enable. The MCH is enabled to generate SERR messages over HI for
specific Device 0 error conditions that are individually enabled in the Hub
Interface SERR Command register (D0:F1:5Ch), System Bus SERR
Command register (D0:F1:6Ch), Memory Buffer SERR Command
register(D0:F1:7Ch), and the DRAM SERR Command register (D0:F1:8Ch).
NOTE: This bit only controls SERR messaging for the Device 0 Function 1 error
conditions not handled by the Device 0 Function 0 SERR enable bit. Devices 1-7
have their own SERR bits to control error reporting for error conditions occurring
on their respective devices. The control bits are used in a logical OR manner to
enable the SERR HI message mechanism.
7:0 0b Reserved
Bit Field
Default &
Access
Description
15 0b Reserved
14 0b
R/WC
Signaled System Error (SSE).
0 = SERR not generated by MCH Device 0
1 = MCH Device 0 generated a SERR
Software clears this bit by writing a ‘1’ to the bit location.
13:0 000h Reserved