Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 75
Register Descriptions
3.6.1 VID – Vendor Identification (D0:F1)
Address Offset: 00 – 01h
Access RO
Size 16 Bits
Default 8086h
The VID register contains the vendor identification number. This register combined with the
Device Identification register uniquely identify any PCI device.
3.6.2 DID – Device Identification (D0:F1)
Address Offset: 02 – 03h
Access RO
Size 16 Bits
Default 3591h
This 16-bit register combined with the Vendor Identification register uniquely identifies any PCI
device.
C2 – C3h THRESH_DED DED Threshold R/W 0000h
C8 – CBh DRAM_SEC2_ADD DRAM Next SEC Address RO 0000_0000h
CC – CDh DRAM_SEC_D0B DIMM 0 Channel B SEC Counter R/W 0000h
CE – CFh DRAM_DED_D0B DIMM 0 Channel B DED Counter R/W 0000h
D0 – D1h DRAM_SEC_D1B DIMM 1 Channel B SEC Counter R/W 0000h
D2 – D3h DRAM_DED_D1B DIMM 1 Channel B DED Counter R/W 0000h
D4 – D5h DRAM_SEC_D2B DIMM 2 Channel B SEC Counter R/W 0000h
D6 – D7h DRAM_DED_D2B DIMM 2 Channel B DED Counter R/W 0000h
D8 – D9h DRAM_SEC_D3B DIMM 3 Channel B SEC Counter R/W 0000h
DA – DBh DRAM_DED_D3B DIMM 3 Channel B DED Counter R/W 0000h
DC – DDh DIMM_THR_EX DIMM Threshold Exceeded R/WC 0000h
E0 – E3h SYSBUS_ERR_CTL System Bus Error Control R/W 0020_0000h
E4 – E7h HI_ERR_CTL Hub Interface Error Control R/W 0004_0000h
E8 – EBh BUFF_ERR_CTL BUFF Error Control R/W 0000_0000h
EC – EFh DRAM_ERR_CTL DRAM Error Control R/W 0000_0000h
Table 3-5. Error Reporting PCI Configuration Register Map (D0:F1) (Sheet 3 of 3)
Address
Offset
Mnemonic Register Name Access Default
Bit Field
Default &
Access
Description
15:0 8086h
RO
Vendor Identification (VID). The PCI standard identification for Intel.
Bit Field
Default &
Access
Description
15:0 3591h
RO
Device Identification Number (DID). This is a value assigned to the MCH
Host-HI Bridge Function 1.
