Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 71
Register Descriptions
3.5.36 REMAPOFFSET – Remap Offset (D0:F0)
Address Offset: CA – CBh
Access: R/W
Size: 16 Bits
Default: 0000h
This register contains the difference between the REMAPBASE and TOLM.
3.5.37 TOM – Top of Memory Register (D0:F0)
Address Offset: CC – CDh
Access: R/W
Size: 16 Bits
Default: 0000h
BIOS uses this register to determine the memory size reported to the OS. The value in this register
hides any DIMMs that can’t be directly addressed due to sparing or mirroring.
3.5.38 EXPECBASE – PCI Express Enhanced Configuration Base
Address Register (D0:F0)
Address Offset: CE – CFh
Access: R/WO
Size: 16 Bits
Default: E000h
Bit Field
Default &
Access
Description
15:10 0 Reserved
9:0 00h
R/W
Remap Limit Address [35:26]. The value in this register defines the upper
boundary of the remap window. The remap window is inclusive of this address. In
the decoder A[25:0] of the Remap Limit Address are assumed to be F’s. Thus the
top of the defined range will be one less than a 64-MB boundary.
When the value in this register is less than the value programmed into the Remap
Base register, the remap window is disabled.
Bit Field
Default &
Access
Description
15:10 0 Reserved
9:0 000h
R/W
Remap Offset. This register contains the difference between the REMAPBASE
and TOLM. This register value corresponds to address bits 35:26. It is used to
translate the physical host-bus address to the system memory address for
accesses to the remap region.
Bit Field
Default &
Access
Description
15:9 0 Reserved
8:0 00h
R/W
Top of Memory (TOM). This field reflects the effective size of memory, taking into
account sparing or mirroring. These bits correspond to address bits 35:27
(128-MB granularity). Bits 26:0 are assumed to be 0.
