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QGE7520MC-SL8EE

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型号: QGE7520MC-SL8EE
PDF文件:
  • QGE7520MC-SL8EE PDF文件
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功能描述: Intel® E7520 Memory Controller Hub (MCH)
PDF文件大小: 2594.09 Kbytes
PDF页数: 共282页
制造商: INTEL[Intel Corporation]
制造商LOGO: INTEL[Intel Corporation] LOGO
制造商网址: http://www.intel.com
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120%
70 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
3.5.34 REMAPBASE – Remap Base Address Register (D0:F0)
Address Offset: C6 – C7h
Access: R/W
Size: 16 Bits
Default: 03FFh
3.5.35 REMAPLIMIT – Remap Limit Address Register (D0:F0)
Address Offset: C8 – C9h
Access: R/W
Size: 16 Bits
Default: 0000h
Bit Field
Default &
Access
Description
15:11 00001b
R/W
Top of Low Memory (TOLM). This register corresponds to bits 31 to 27 of the
system address which is 1 greater than the maximum DRAM location below 4GB.
Configuration software should set this value to either the maximum amount of
memory in the system or to the minimum address allocated for PCI memory or
the graphics aperture, whichever is smaller. Address bits 26:0 are assumed to be
0 for the purposes of address comparison. Addresses equal to or greater than the
TOLM, and less than 4G, are treated as non-memory accesses. All accesses less
than the TOLM are treated as DRAM accesses (except for the 15-16MB or PAM
gaps).
This register must be set to at least 0800h, for a minimum of 128MB of DRAM.
There is also a minimum of 128MB of PCI space, since this register is on a
128MB boundary.
Configuration software should set this value to either the maximum amount of
memory in the system (same as DRB7), or to the lower 128MB boundary of the
Memory Mapped IO range, whichever is smaller.
Programming example: 1100_0b = 3GB (assuming that DBR7 is set > 4GB): An
access to 0_C000_0000h or above (but <4GB) will be considered above the
TOLM and therefore not to DRAM. It may go to PCI Express or the HI or be
subtractively decoded to HI. An access to 0_BFFF_FFFFh and below will be
considered below the TOLM and go to DRAM.
10:0 000h Reserved
Bit Field
Default &
Access
Description
15:10 0 Reserved
9:0 3FFh
R/W
Remap Base Address [35:26]. The value in this register defines the lower
boundary of the remap window. The remap window is inclusive of this address. In
the decoder A[25:0] of the remap Base Address are assumed to be zeros. Thus
the bottom of the defined memory range will be aligned to a 64-MB boundary.
When the value in this register is greater than the value programmed into the
Remap Limit register, the Remap window is disabled.
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