Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 67
Register Descriptions
3.5.30 SMRC – System Management RAM Control Register (D0:F0)
Address Offset: 9Eh
Access: RO, R/W, R/W/L, R/WS
Size: 8 Bits
Default: 02h
This register controls how accesses to Compatible and Extended SMRAM spaces are treated. The
open, close, and lock bits function only when G_SMRAME bit is set to ‘1’. The open bit must be
reset before the lock bit is set.
4 0b
R/W
Hub Interface RCOMP Disable.
0 = Enable the RCOMP operation for the Hub Interface.
1 = Disable the RCOMP operation for the Hub Interface.
3 0b
R/W/L
Global SMRAM Enable (G_SMRAME).
0 = Disable
1 = Enable compatible and extended SMRAM functions. Provides 128 KB of
DRAM accessible at the A0000h address while in SMM (ADS# with SMM
decode). Refer to the section on SMM for more details.
Note: Once D_LCK is set, this bit becomes read only.
2:1 00b
R/W/L
TSEG Size (TSEG_SZ). Selects the size of the TSEG memory block if enabled.
Memory from the top of DRAM space (TOLM – TSEG_SZ) to TOLM is partitioned
away so that it may only be accessed by the processor interface and only then
when the SMM bit is set in the request packet. Non-SMM accesses to this
memory region are sent to HI when the TSEG memory block is enabled. Note
that once D_LCK is set, these bits become read only.
0 0= (TOLM – 128 k) to TOLM
0 1= (TOLM – 256 k) to TOLM
1 0= (TOLM – 512 k) to TOLM
1 1= (TOLM – 1 M) to TOLM
0 0b
R/W/L
TSEG Enable (TSEG_EN). Enabling of SMRAM memory for Extended SMRAM
space only.
0 = Disable TSEG
1 = TSEG appears in the appropriate physical address space (only when
G_SMRAME = 1).
Note: Once D_LCK is set, this bit becomes read only.
Bit Field
Default &
Access
Description
Bits
Default &
Access
Description
7 0b Reserved
6 0b
R/W/L
SMM Space Open (D_OPEN). When D_OPEN=1 and D_LCK=0, the SMM space
DRAM is made visible even when SMM decode is not active. This is intended to help
BIOS initialize SMM space. Software should ensure that D_OPEN=1 and D_CLS=1 are
not set at the same time.
Note: This bit becomes RO when D_LCK is set to ‘1’.
5 0b
R/W
SMM Space Closed (D_CLS). When D_CLS = 1 SMM space DRAM is not accessible
to data references, even if SMM decode is active. Code references may still access
SMM space DRAM. This will allow SMM software to reference through SMM space to
update the display even when SMM is mapped over the VGA range. Software should
ensure that D_OPEN=1 and D_CLS=1 are not set at the same time.
Note: The D_CLS bit only applies to Compatible SMM space.
