66 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
3.5.29 ESMRC – Extended System Management RAM Control
(D0:F0)
Address Offset: 9Dh
Access: R/W/L, R/W
Size: 8 Bits
Default: 00h
The Extended SMRAM register controls the configuration of Extended SMRAM space. The
Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM memory
space that is above 1 Mbyte.
Bit Field
Default &
Access
Description
7 0b
R/W/L
Enable High SMRAM (H_SMRAME). Controls the SMM memory space location
(i.e. above 1 Mbyte or below 1 Mbyte).
0 = Disable High SMRAM
1 = Enable High SMRAM memory space. (only when G_SMRAME is ‘1’).
SMRAM accesses within the range 0FEDA_0000h to 0FEDA_FFFFh are
remapped to DRAM addresses within the range 000A0000h to 000BFFFFh.
Note: Once D_LCK has been set, this bit becomes read only.
6 0b
R/W
MDA Present (MDAP). This bit works with the VGA Enable bits in the BCTRL
registers of Devices 2–7 to control the routing of processor-initiated transactions
targeting MDA compatible I/O and memory address ranges. This bit should not
be set if none of the VGA Enable bits are set. If none of the VGA enable bits are
set, then accesses to I/O address range x3BCh – x3BFh are forwarded to the HI.
If the VGA enable bit is not set then accesses to I/O address range x3BCh –
x3BFh are treated just like any other I/O accesses, i.e., the cycles are forwarded
to PCI Express if the address is within the corresponding IOBASE and IOLIMIT
and ISA enable bit is not set, otherwise they are forwarded to HI.
NOTE: Since the logic performs address decoding on a DW boundary, the DW
that includes address 3BFh also includes addresses 3BCh, 3BDh and 3BEh, and
accesses to any of these byte addresses are handled as MDA references.
MDA resources are defined as the following:
Memory: 0B0000h – 0B7FFFh
I/O: 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh, (including ISA address aliases,
A[15:10] are not used in decode)
NOTE: The VGA region includes I/O space ranges 3B0 – 3BBh and 3C0 – 3DF,
so there is an overlap between these two I/O regions.
Any I/O reference that includes the I/O locations listed above, or their aliases, will
be forwarded to Hub Interface even if the reference includes I/O locations not
listed above.
The following table shows the behavior for all combinations of MDA and VGA:
VGA MDA Behavior
0 0 All References to MDA and VGA go to HI
0 1 Illegal Combination (DO NOT USE)
1 0 All References to VGA go to device with VGA enable set. MDA-
only references (I/O address 3BF and aliases) will go to HI.
1 1 VGA-only references go to the PCI Express port which has its
VGA Enable bit set. MDA References go to the HI
5 0b
R/W
APIC Memory Range Disable (APICDIS). When set to ‘1’, the MCH forwards
accesses to the IOAPIC regions to the appropriate interface, as specified by the
memory and PCI configuration registers. When this bit is clear, the MCH will send
cycles between 0_FEC0_0000 and 0_FEC7_FFFF to the HI. Accesses between
0_FEC8_0000 and 0_FEC8_0FFF will be sent to PCI Express A,
between 0_FEC8_1000 and 0_FEC8_1FFF will be sent to PCI Express A1,
between 0_FEC8_2000 and 0_FEC8_2FFF will be sent to PCI Express B,
between 0_FEC8_3000 and 0_FEC8_3FFF will be sent to PCI Express B1,
between 0_FEC8_4000 and 0_FEC8_4FFF will be sent to PCI Express C, and
between 0_FEC8_5000 and 0_FEC8_5FFF will be sent to PCI Express C1.
