64 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
9 0b
R/W
DIMM Sparing Enable.
0 = Disable on-line DIMM sparing and enables symmetric decode
1 = Enable on-line DIMM sparing and disables symmetric decode
8:7 00b
R/W
Failing DIMM. Used to specify the copy source for DIMM sparing. The encoding
for this two-bit field shown is for the logical CS pair. Note that setting these bits by
themselves does not initiate data migration. For the copy to commence, the
Transition Enable bit must be set.
00 = CS pair 0 and 1
01 = CS pair 2 and 3
10 = CS pair 4 and 5
11 = CS pair 6 and 7
6:5 00b Reserved
4 0b
R/O
Symmetric Mode. The DRAM logic when it detects that it is not in mirrored or
sparing mode, and it has four equal ranks, puts the DIMMs into interleaved mode
for improved performance. This state is reflected for use by BIOS.
0 = Disable Symmetric Mode (enable interleaved mode)
1 = Enable Symmetric Mode (disable interleaved mode)
3:0 0h
RO
Channel Configuration FSM Current State. This field details the current state of
the DDRCSR_FSM.
0000 – Idle
0100 – Single channel A normal
0101 – Single channel A sparing copy in progress
0111 – Single channel A sparing complete
1000 – Single channel B normal
1001 – Single channel B sparing copy in progress
1011 – Single channel B sparing complete
1100 – Dual channel normal
1101 – Dual channel sparing copy in progress
1111 – Dual channel sparing complete
1010 – Mirrored dual channel state (read01)
1110 – Mirrored dual channel state (read10)
Bit Field
Default &
Access
Description
