Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 61
Register Descriptions
3.5.23 ECCDIAG – ECC Detection /Correction Diagnostic Register
(D0:F0)
Address Offset: 84 – 87h
Access: R/W, RO, R/WS
Size: 32 Bits
Default: 0000_0000h
This register is used for diagnostic testing of ECC from the DRAM. This feature is presented for
validation purposes only. Functionality is not guaranteed and may not be supported.
3.5.24 SDRC – DDR SDRAM Secondary Control Register (D0:F0)
Address Offset: 88 - 8Bh
Access: RO, R/W
Size: 32 bits
Default Value: 0000_0000h
Bit Field
Default &
Access
Description
31:18 000h Reserved
18 0b
R/W
Memory Poison Enable. Allows for propagation of data errors not initiated by this
register to DRAM. Error Injection is possible regardless of this bit setting. The
setting of this bit has no effect on the reporting or logging of data errors.
0 = Error poisoning is disabled. Bad ECC arriving at the Memory Interface
(Inbound, during memory writes), will be recalculated based on the data, and
then, forwarded to the memory.
1 = Error poisoning enabled. Bad ECC arriving at the Memory Interface
(Inbound, during memory writes), will be forwarded as bad ECC to the
Memory.
17:0 00000h Reserved
Bit Field Default & Access Description
31:30 00b
R/W
Channel B On Die Termination Enable. Enables the MCH on-die
termination for the DDR2 channel B data signals. The MCH terminates the
DQ/DQS signals for a read. The MCH has ODT regardless of its operating
in either DDR or DDR2 mode even though of the two types of memory
devices, only DDR2 has ODT. The termination values are dependent on the
DDRIMPCRES external resistor (Rodt).
Encoding DDR MCH ODT DDR2 MCH ODT
(Rodt=383) (Rodt=287)
00 Off Off
01 (Rodt/2)~200 150
10 (Rodt/4)~200 150
11 ~100 ~75
29:28 00b
R/W
Channel A On Die Termination Enable. These bits enable the MCH
on-die termination for the DDR2 channel A data signals. Encodings match
those provided above for channel B.
27:9 0_0000h Reserved