60 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
3.5.22 DRORC – Opportunistic Refresh Control Register (D0:F0)
Address Offset: 82h
Access: R/W
Size: 8 Bits
Default: 71h
The MCH contains a 4b refresh counter that allows the counting of up to 16 refreshes. Using the
counter, refresh requests can be queued when the DRAM interface is busy performing cycles.
Ideally, refreshes are performed when the DRAM interface is idle. This opportunistic refresh
scheme utilizes two watermarks, which the following register is used to control.
Bit Field
Default &
Access
Description
7:4 0111b
R/W
High Watermark. When the refresh-counter reaches or exceeds the value in the
high watermark field, the DRAM controller performs a refresh in the highest
priority mode. In such a case, refresh will be processed as soon as the currently
pending DRAM cycle is completed. Once a high priority refresh is internally
launched (through the command queue), the DRAM controller may schedule an
additional refresh immediately if the refresh counter high watermark condition
remains “true”.
Note that current DDR components require DLL refresh every 9 refresh periods.
As a result, this register must be set at 7 or lower.
Bit field encoding:
0000 Illegal value
0001 One Refresh is the watermark
……
1111 15 Refreshes is the watermark
3:0 0001b
R/W
Low Watermark. When the refresh-counter reaches or exceeds the value in the
low watermark field, the DRAM controller performs a refresh if there is no other
request pending to DRAM. It means that low watermark refresh is performed as
the lowest priority request, opportunistically. Once a low priority refresh is
internally launched (through the command queue), the DRAM controller will not
schedule an additional low priority refresh until the already launched refresh
operation is completed (low watermark refresh is blocked when the command
queue contains a low watermark refresh request). Once low watermark refresh
counter is reached or exceeded, the DRAM controller will opportunistically
perform low priority refreshes until the refresh counter is down to 0.
Bit field encoding:
0000 Illegal value
0001 One Refresh is the watermark
……
1111 15 Refreshes is the watermark
