Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 57
Register Descriptions
Bit Field
Default &
Access
Description
31:30 00b
RO
Revision Number (REV). The DDR register definition format revision number.
This field is reserved and will always return zeroes when read.
29 0b
R/W
Initialization Complete (IC). This bit is used for communication of software state
between the memory controller and the BIOS.
0 = The DRAM interface has NOT been initialized.
1 = The DRAM interface has been initialized.
28 0b
R/W
Dynamic Power-Down Mode Enable. When set, the DRAM controller will put
pair of rows into power down mode when all banks are precharged (closed). Once
a bank is accessed, the relevant pair of rows is taken out of Power Down mode.
DIMM power down mode is controlled by the CKE signal.
0 = DRAM Power-down disabled (DDR, DDR2 with ODT)
1 = DRAM Power-down enabled (DDR)
27 0b
R/W
DED Retry Enable.
0 = Disabled. No retries occur on double-bit errors.
1 = Enable a single retry of read accesses on detection of a double-bit error.
26 0b
R/W
Overlap Enable.
0 = Inhibits overlap scheduling of row/col tenures.
1 = Allows overlapped scheduling of activates prior to completing the
outstanding column command.
25:24 00b
R/W
Auto-Precharge Mode for Writes.
00 = Intelligent
01 = Always Auto-precharge
10 = Never Auto-precharge
11 = Reserved
23:22 00b
R/W
Auto-Precharge Mode for Reads.
00 = Intelligent
01 = Always Auto-precharge
10 = Never Auto-precharge
11 = Reserved
21:20 00b
R/W
DRAM Data Integrity Mode (DDIM). These bits select one of four DRAM data
integrity modes. When in non-ECC mode, no ECC correction is done and no ECC
errors are logged in the FERR/NERR registers.
NOTE 1: Non-ECC mode should be used for debug purposes only, and non-ECC
DIMMs are not supported.
NOTE 2: If mode 10b (x4 SDDC) is selected in single channel mode, the MCH will
effectively change this to 01 and enforce 72-bit ECC.
00 = Non-ECC mode.
01 = 72-bit ECC
10 = x4 Chip-Fail ECC
11 = Reserved
19:11 000h Reserved