56 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
3.5.20 DRC – DRAM Controller Mode Register (D0:F0)
Address Offset: 7C – 7Fh
Access: RO, R/W, R/WO
Size: 32 Bits
Default: 0000_0008h
This register controls the mode of the DRAM controller.
9:8 10b
R/W
DRAM RAS# Precharge (Trp). This bit controls the number of clocks that are
inserted between a row precharge command and an activate command to the
same row.
Encoding Number of CMDCLK at Specified Frequency
133 MHz 167MHz 200 MHz
00 Reserved Reserved Reserved
01 2 (15 ns) 2 (12 ns) 3 (15 ns)
10 3 (22.5 ns) 3 (18 ns) 4 (20 ns)
11 Reserved Reserved Reserved
7:6 00b
R/W
Back-To-Back Write Turn Around. This field determines the data bubble
duration between Write data bursts. It applies to WR-WR pairs to different ranks,
and is only expected to be used in DDR2 mode with ODT enabled in the event
that ODT selections must change between ranks. The purpose of this field is to
control the data burst spacing on the DQ bus.
Encoding Number of CMDCLK at Specified Frequency
133 MHz 167MHz 200 MHz
00 0 (0 ns) 0 (0 ns) 0 (0 ns)
01 1 (7.5 ns) 1 (6 ns) 1 (5 ns)
10 2 (15 ns) 2 (12 ns) 2 (10 ns)
11 Reserved Reserved 3 (15 ns)
5 0b
R/W
Turn Around Cycle Add. Setting this bit to a ‘1’ adds an extra turn around cycle
between a read to DIMM4 (furthest DIMM from MCH) and a read to DIMM1
(nearest DIMM to MCH). It is only intended for use in a 4 DIMM configuration
where the farthest logical DIMM is also the farthest physical DIMM (DRM setting
of 1248h).
4 0b
R/W
CKE Guard Band.
0 = CKE is driven high for one CMDCLK prior to a new command
1 = CKE is driven high for two CMDCLKs prior to a new command
3:2 01b
R/W
CAS# Latency (Tcl). The number of clocks between the rising edge used by
DRAM to sample the Read Command and the rising edge that is used by the
DRAM to drive read data.
Encoding Number of CMDCLK at Specified Frequency
133 MHz 167MHz 200 MHz
00 2 or 2.5 2 or 2.5 Reserved
01 Reserved Reserved 3
10 3 3 4
11 Reserved Reserved Reserved
1:0 00b
R/W
CKE Idle Selection. Specifies the number of CMDCLKs with no command
activity to a row before deasserting CKE, putting the row into low power mode.
Encoding Number of CMDCLK at Specified Frequency
133 MHz 167MHz 200 MHz
00 32 32 32
01 128 128 128
10 512 512 512
11 2K 2K 2K
Bit Field
Default &
Access
Description
