Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 55
Register Descriptions
21:20 01b
R/W
Row Delay (Trrd). The required row delay period between two activate
commands accessing the same CS# of a DIMM.
Encoding Number of CMDCLK at Specified Frequency
133 MHz 167MHz 200 MHz
00 1 (7.5 ns) 1 (6 ns) 1 (5 ns)
01 2 (15 ns) 2 (12 ns) 2 (10 ns)
10 3 (22.5 ns) 3 (18 ns) 3 (15 ns)
11 Reserved Reserved 4 (20 ns)
19:18 10b
R/W
Trasmax. Indicates allowable number of clocks to allow sequential page hits prior
to forcing a precharge to close the page.
Encoding Number of CMDCLK at Specified Frequency
133 MHz 167MHz 200 MHz
00 32 32 32
01 64 64 64
10 128 128 128
11 512 512 512
17:16 01b
R/W
Write Recovery Delay (Twr). The required write recovery delay before being
able to issue a precharge to the same page accessing the same CS/bank of a
DIMM.
Encoding Number of CMDCLK at Specified Frequency
133 MHz 167MHz 200 MHz
00 Reserved Reserved Reserved
01 2 (15 ns) 2 (12 ns) Reserved
10 Reserved 3 (18 ns) 3 (15 ns)
11 Reserved Reserved 4 (20 ns)
15:14 10b
R/W
RAS Cycle Time (Trc). These bits control the required delay from an activate
command before issuing another activate or refresh command to the same
CS/bank of a DIMM.
Encoding Number of CMDCLK at Specified Frequency
133 MHz 167MHz 200 MHz
00 Reserved Reserved 11 (55 ns)
01 Reserved Reserved 12 (60 ns)
10 9 (67.5 ns) 10 (60 ns) 13 (65 ns)
11 Reserved Reserved Reserved
13:12 01b
R/W
Write with Auto precharge Recovery Delay (Tdal). The time required before
being able to issue an activate command to the same page accessing the same
CS / Bank of a DIMM. The value must be the sum of Trp and Twr (Tdal = Trp +
Twr).
Encoding Number of CMDCLK at Specified Frequency
133 MHz 167MHz 200 MHz
00 Reserved Reserved 6 (30 ns)
01 5 (37.5 ns) 5 (30 ns) 7 (35 ns)
10 Reserved 6 (36 ns) Reserved
11 Reserved Reserved Reserved
11:10 01b
R/W
Write RAS# to CAS# Delay (Trcd). Controls the number of clocks inserted
between a row activate command and a read or write command to that row
Encoding Number of CMDCLK at Specified Frequency
133 MHz 167MHz 200 MHz
00 2 (15 ns) 2 (12 ns) 3 (15 ns)
01 3 (22.5 ns) 3 (18 ns) 4 (20 ns)
10 Reserved Reserved Reserved
11 Reserved Reserved Reserved
Bit Field
Default &
Access
Description
