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QGE7520MC-SL8EE

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型号: QGE7520MC-SL8EE
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  • QGE7520MC-SL8EE PDF文件
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功能描述: Intel® E7520 Memory Controller Hub (MCH)
PDF文件大小: 2594.09 Kbytes
PDF页数: 共282页
制造商: INTEL[Intel Corporation]
制造商LOGO: INTEL[Intel Corporation] LOGO
制造商网址: http://www.intel.com
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54 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
3.5.19 DRT – DRAM Timing Register (D0:F0)
Address Offset: 78 – 7Bh
Access: R/W
Size: 32 Bits
Default: 9599_9604h
This register controls the timing of the DRAM Interface.
Bit Field
Default &
Access
Description
31:30 10b
R/W
Programmable Read Pointer Delay. This bit determines the read pointer delay,
which is based on both DIMM topology and technology. The encodings in this
table refer to additional delays beyond one command clock.
Encoding Number of CMDCLK at Specified Frequency
133 MHz 167MHz 200 MHz
00 0 (0 ns) 0 (0 ns) 0 (0 ns)
01 1 (7.5 ns) 1 (6 ns) 1 (5 ns)
10 2 (15 ns) 2 (12 ns) 2 (10 ns)
11 Reserved Reserved Reserved
29:28 01b
R/W
Back-To-Back Write-Read Turn Around. This field determines the data bubble
duration in CMDCLKs between Write-Read commands. It applies toward WR-RD
pairs to any destinations (in same or different rows). The purpose of this bit is to
control the turnaround time on the DQ bus.
Encoding Number of CMDCLK at Specified Frequency
133 MHz 167MHz 200 MHz
00 Reserved Reserved Reserved
01 1 (7.5 ns) 1 (6 ns) 1 (5 ns)
10 2 (15 ns) 2 (12 ns) 2 (10 ns)
11 Reserved Reserved 3 (15 ns)
27:26 01b
R/W
Back-To-Back Read-Write Turn Around. This field determines the minimum
number of CMDCLK between Read-Write commands. It applies toward RD-WR
pairs to any destinations (in same or different rows). The purpose of this bit is to
control the turnaround time on the DQ bus.
Encoding Number of CMDCLK at Specified Frequency
133 MHz 167MHz 200 MHz
00 1 (7.5 ns) 1 (6 ns) 1 (5 ns)
01 2 (15 ns) 2 (12 ns) 2 (10 ns)
10 3 (22.5 ns) 3 (18 ns) 3 (15 ns)
11 4 (30 ns) 4 (24 ns) 4 (20 ns)
25:24 01b
R/W
Back To Back Read Turn Around. This field determines the minimum number of
CMDCLK between two Reads destined to different rows. The purpose of these
bits is to control the turnaround time on the DQ bus.
Encoding Number of CMDCLK at Specified Frequency
133 MHz 167MHz 200 MHz
00 Reserved Reserved Reserved
01 1 (7.5 ns) 1 (6 ns) 1 (5 ns)
10 2 (15 ns) 2 (12 ns) 2 (10 ns)
11 Reserved Reserved 3 (15 ns)
23:22 10b
R/W
Auto refresh Cycle Time (Trfc). The required time between/after auto refresh
cycles to any particular DIMM.
Encoding Number of CMDCLK at Specified Frequency
133 MHz 167MHz 200 MHz
00 10 (75 ns) 12 (72 ns) 15 (75 ns)
01 Reserved Reserved 21 (105 ns)
10 16 (120 ns) 20 (120 ns) 26 (130 ns)
11 Reserved Reserved Reserved
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