50 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
3:2 00b Reserved
1:0 00b
R/W
Low Attribute Register (LOENABLE). This field controls the steering of read
and write cycles that address the BIOS
0 0= DRAM Disabled – All accesses are directed to the HI
0 1= Read Only – All reads are serviced by DRAM. Writes are forwarded to HI
1 0= Write Only – All writes are sent to DRAM. Reads are serviced by the HI
1 1= Normal DRAM Operation – All reads and writes are serviced by DRAM
NOTE: The Low segment for PAM0 is Reserved, as shown in Figure 3-5
Figure 3-5. PAM Associated Attribute Bits
Bit Field
Default &
Access
Description
PAM6 5Fh
PAM1
PAM2
PAM3
PAM4
PAM5
5Ah
5Bh
5Ch
5Dh
5Eh
Offset
WERRRER W E RER
7 0123456
Reserved
Reserved
Write Enable (R/W)
1 = Enable
0 = Disable
Read Enable (R/W )
1 = Enable
0 = Disable
Reserved
Reserved
Write Enab le (R/W)
1 = Enable
0 = Disable
Read Enable (R/W )
1 = Enable
0 = Disable
59hPAM0
HI Segment LO Segment
Reserved