Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 49
Register Descriptions
3.5.16 PAM 0:6 – Programmable Attribute Map Registers 0 – 6
(D0:F0)
Address Offset: 59 – 5Fh (PAM0 – PAM6)
Access: R/W,RO
Size: 8 Bits Each
Default: 00h
The MCH allows programmable memory attributes on 13 legacy memory segments of various
sizes in the 768 KB to 1 MB (C0000h – FFFFFh) address range. Seven Programmable Attribute
Map (PAM) registers are used to support these features. Not all seven of these registers are
identical. PAM0 controls only one segment (high), while PAM[1:6] each control two segments
(high and low). Cacheability of these areas is controlled via the MTRR registers in the processor.
The following two bits are used to specify the memory attributes for each memory segment:
RE Read Enable. When RE = 1, the processor read accesses to the corresponding memory segment are
claimed by the MCH and directed to main memory. Conversely, when RE = 0, the host read accesses
are directed to PCI_A.
WE Write Enable. When WE = 1, the host write accesses to the corresponding memory segment are claimed
by the MCH and directed to main memory. Conversely, when WE = 0, the host write accesses are
directed to PCI_A.
Together, these two bits specify memory attributes (Read Only, Write Only, Read/Write and
Disabled) for each memory segment. These bits only apply to host-initiated access to the PAM
areas. The MCH forwards to main memory any PCI Express initiated accesses to the PAM areas.
At the time such PCI Express accesses to the PAM region may occur, the targeted PAM segment
must be programmed to Read/Write. It is illegal to issue a PCI Express initiated transaction to a
PAM region with the associated PAM register not set to Read/Write.
As an example, consider a BIOS that is implemented on the expansion bus. During the
initialization process, BIOS can be shadowed to main memory to increase system performance.
When BIOS is shadowed to main memory it should be copied to the same address location. To
shadow the BIOS, the attributes for that address range should be set to Write Only. The BIOS is
shadowed by first doing a read of that address, which is forwarded to the expansion bus. The host
then does a write of the same address, which is directed to main memory. After BIOS is completely
shadowed, the attributes for that memory area are changed to Read Only so that all writes are
forwarded to the expansion bus. Figure 3-5 and Table 3-3 show the PAM registers and the
associated attribute bits.
Bit Field
Default &
Access
Description
7:6 00b Reserved
5:4 00b
R/W
High Attribute Register (HIENABLE). This field controls the steering of read and
write cycles that address the BIOS
0 0= DRAM Disabled – All accesses are directed to the HI
0 1= Read Only – All reads are serviced by DRAM. Writes are forwarded to HI
1 0= Write Only – All writes are sent to DRAM. Reads are serviced by the HI
1 1= Normal DRAM Operation – All reads and writes are serviced by DRAM
