Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 43
Register Descriptions
3.5.3 PCICMD – PCI Command Register (D0:F0)
Address Offset: 04 – 05h
Access: RO, R/W
Size: 16 Bits
Default: 0006h
Since MCH Device 0 does not physically reside on a real PCI bus, portions of this register are not
implemented.
3.5.4 PCISTS – PCI Status Register (D0:F0)
Address Offset: 06 – 07h
Access: R/WC, RO
Size: 16 Bits
Default: 0090h
Bit Field
Default &
Access
Description
15:10 00h Reserved
9 0b
RO
Fast Back-to-Back Enable (FB2B).This bit controls whether or not the master can do
a fast back-to-back write. Since Device 0 is strictly a target, this bit is hardwired to ‘0’.
8 0b
R/W
SERR Enable (SERRE). This is a global enable bit for Device 0 SERR messaging.
The MCH does not have an SERR signal. The MCH communicates the SERR
condition by sending an SERR message over the HI to the ICH.
0 = Disable. The SERR message is not generated by the MCH for Device 0.
1 = Enable. The MCH is enabled to generate SERR messages over HI for specific
Device 0 error conditions that are individually enabled in the HI_SERRCMD
register (D0:F1:5Ch).
NOTE: This bit only controls SERR messaging for the following Device 0 errors: Hub
Interface Data Parity Errors and Hub Interface Address/Command Parity Errors.
These errors are reported via the Hub Interface SERR Command registers
(HI_SERRCMD, Bus 0, Device 0, Function 1, Offset 5Ch, bit 4 and 0 respectively).
Devices 1-7 have their own SERR bits to control error reporting for error conditions
occurring on their respective devices. The control bits are used in a logical OR manner
to enable the SERR HI message mechanism.
7 0b
RO
Address/Data Stepping Enable (ADSTEP). Address/data stepping is not
implemented in the MCH.
6 0b
R/W
Parity Error Enable (PERRE).
0 = Disable. The MCH does not take any action when it detects a parity error on HI.
1 = Enable. The MCH generates an SERR message over the HI to the ICH when an
address or data parity error is detected by the MCH on the HI (DPE set in
PCISTS) and SERRE is set to ‘1’.
5 0b
RO
VGA Palette Snoop Enable (VGASNOOP). The MCH does not implement this bit.
4 0b
RO
Memory Write and Invalidate Enable (MWIE). The MCH will never issue memory
write and invalidate commands.
3 0b
RO
Special Cycle Enable (SCE). The MCH does not implement this bit.
2 1b
RO
Bus Master Enable (BME). The MCH is always enabled as a master, so this bit is
hardwired to ‘1’.
1 1b
RO
Memory Access Enable (MAE). This bit is hardwired to ‘1’.
0 0b
RO
I/O Access Enable (IOAE). This bit is not implemented in the MCH.
