Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 41
Register Descriptions
3.5 MCH Control Registers (D0:F0)
The MCH Control registers are in Device 0 (D0), Function 0 (F0). Table 3-2 provides the register
address map for this device and function.
Warning: Address locations that are not listed are considered Reserved register locations. Reads to Reserved
registers may return non-zero values. Writes to reserved locations may cause system failure.
Table 3-2. MCH Control PCI Configuration Register Map (D0:F0) (Sheet 1 of 2)
Offset Mnemonic Register Name Access Default
00 – 01h VID Vendor Identification RO 8086h
02 – 03h DID Device Identification RO 3590h
04 – 05h PCICMD PCI Command Register RO, R/W 0006h
06 – 07h PCISTS PCI Status Register R/WC, RO 0090h
08h RID Revision Identification RO 09h
0Ah SUBC Sub-Class Code RO 00h
0Bh BCC Base Class Code RO 06h
0Dh MLT Master Latency Timer RO 00h
0Eh HDR Header Type RO 00h
2C – 2Dh SVID Subsystem Vendor Identification R/WO 0000h
2E – 2Fh SID Subsystem Identification R/WO 0000h
34h CAPPTR Capabilities Pointer RO 40h
50h MCHCFG0 MCH Configuration 0 RO 0Ch
52 – 53h MCHSCRB MCH Memory Scrub and Init Configuration RO, R/W 0000h
58h FDHC Fixed DRAM Hole Control R/W, RO 00h
59 – 5Fh PAM 0:6 Programmable Attribute Map 0 – 6 R/W, RO 00h
60 – 67h DRB 0:7 DRAM Row Boundary Register 0 – 7 R/W 00h
70 – 73h DRA 0:3 DRAM Row Attribute Register 0 – 3 R/W 00h
78 – 7Bh DRT DRAM Timing Register R/W 9599_9604h
7C – 7Fh DRC DRAM Controller Mode Register RO, R/W,
R/WO
0000_0008h
80 – 81 DRM DRAM Mapping Register R/W 8421h
82 DRORC Opportunistic Refresh Control Register R/W 71h
84 – 87h ECCDIAG ECC Detection/Correction Diagnostic Register R/W, RO,
R/WS
0000_0000h
88 – 8Bh SDRC DDR SDRAM Secondary Control Register R/W 0000_0000h
8Ch CKDIS CK/CK# Disable R/W FFh
8Dh CKEDIS CKE/CKE# Disable R/W 00h
9A – 9Bh DDRCSR DDR Channel Configuration Control/Status
Register
RO, R/WS,
R/W
0000h
9Ch DEVPRES Device Present R/WO,RO 03h
9Dh ESMRC Extended System Management RAM Control R/W/L, R/W 00h
9Eh SMRC System Management RAM Control R/W, RO,
R/W/L, R/WS
02h
9Fh EXSMRC Expansion System Management RAM Control R/WC, RO 07h
B0 – B3h DDR2ODTC DDR2 ODT Control Register R/W 0000_0000h
C4 – C5h TOLM Top of Low Memory Register R/W 0800h
C6 – C7h REMAPBASE Remap Base Address Register R/W 03FFh