40 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
3.4.1 PCI Express Configuration Transaction Header
The PCI Express Configuration Transaction Header includes an additional four bits for the Register
Number field (ExtendedRegisterAddress[3:0]) to provide additional configuration space.
The PCI 2.3 compatible configuration access mechanism uses the same Request format as the
enhanced PCI Express mechanism. For PCI-compatible Configuration Requests, the Extended
Register Address field must be all zeros.
To maintain compatibility with PCI configuration addressing mechanisms, system software must
access the enhanced configuration space using DWORD operations (DWORD-aligned) only.
3.4.2 Enhanced Configuration Memory Address Map
The Enhanced Configuration Memory Address Map is positioned into memory space by use of the
PCI Express Enhanced Configuration Base register known as EXPECBASE. This register contains
the address that corresponds to bits 31 to 28 of the base address for PCI Express enhanced
configuration space below 4 GB. Configuration software will read this register to determine where
the 256 MB range of memory addresses resides for enhanced configuration. This register defaults
to a value of Eh, which corresponds to E000 0000h. It is not intended that this value is ever
changed by BIOS.
Figure 3-3. PCI Express Configuration Transaction Header
Requester ID
Register
Number
Typex01
1st DW
BE
Et
7 6 3 2 1 045 7 6 3 2 1 045 7 6 3 2 1 045 7 6 3 2 1 045
00000000 0000Reserved
+0
+1
+2 +3
R
Function
Number
Device
Number
Bus Number
Ext. Reg.
Address
Reserved
Reserved Tag
Virtual
Channel ID
Byte 0>
Byte 4>
Byte 8>
Figure 3-4. Enhanced Configuration Memory Address Map
Bus 0
Bus 1
Bus 255
Device 0 Function 0
Device 0 Function 1
Device 0 Function 2
0
0xFFFFF
0x1FFFFF
0xFFFFFFF
Device 1 Function 0
0xFFF
0x1FFF
0x7FFF
0xFFFFF
