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QGE7520MC-SL8EE

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型号: QGE7520MC-SL8EE
PDF文件:
  • QGE7520MC-SL8EE PDF文件
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功能描述: Intel® E7520 Memory Controller Hub (MCH)
PDF文件大小: 2594.09 Kbytes
PDF页数: 共282页
制造商: INTEL[Intel Corporation]
制造商LOGO: INTEL[Intel Corporation] LOGO
制造商网址: http://www.intel.com
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120%
Intel
®
E7520 Memory Controller Hub (MCH) Datasheet 37
Register Descriptions
3.2.1 Standard PCI Bus Configuration Mechanism
The PCI Bus defines a slot-based configuration space that allows each device to contain up to eight
functions; each function containing up to 256, 8-bit configuration registers. The PCI Local Bus
Specification, Rev 2.3 defines two bus cycles to access the PCI configuration space: Configuration
Read and Configuration Write. Memory and I/O spaces are supported directly by the processor.
Configuration space is supported by a mapping mechanism implemented within the MCH.
Previous versions of the PCI Local Bus Specification define two mechanisms to access
configuration space, Mechanism 1 and Mechanism 2. The MCH supports only Mechanism 1.
The configuration access mechanism makes use of the CONFIG_ADDRESS register and
CONFIG_DATA register. To reference a configuration register, a Dword (32-bit) I/O write cycle is
used to place a value into CONFIG_ADDRESS that specifies the PCI bus, the device on that bus,
the function within the device, and a specific configuration register of the device function being
accessed. CONFIG_ADDRESS[31] must be 1 to enable a configuration cycle. CONFIG_DATA
then becomes a window into the four bytes of configuration space specified by the contents of
CONFIG_ADDRESS. Any read or write to CONFIG_DATA will result in the MCH translating the
CONFIG_ADDRESS into the appropriate configuration cycle.
The MCH is responsible for translating and routing the processor's I/O accesses to the
CONFIG_ADDRESS and CONFIG_DATA registers to internal MCH configuration registers for
the HI and PCI Express.
3.2.2 Logical PCI Bus 0 Configuration Mechanism
The MCH decodes the Bus Number (bits 23:16) and the Device Number fields of the
CONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0 the
configuration cycle is targeting a PCI Bus 0 device.
Configuration cycles to any of the MCH’s enabled internal devices are confined to the MCH and
not sent over the HI. Accesses to disabled or non-existent internal devices are forwarded over the
HI as Type 0 Configuration Cycles. The ICH decodes the Type 0 access and generates a
configuration access to the selected internal device.
3.2.3 Primary PCI and Downstream Configuration Mechanism
If the Bus Number in the CONFIG_ADDRESS is non-zero, and does not lie between the
SECONDARY BUS NUMBER register and the SUBORDINATE BUS NUMBER register for one
of the PCI Express bridges, the MCH will generate a Type 1 HI Configuration Cycle.
When the cycle is forwarded to the ICH via the HI, the ICH compares the non-zero Bus Number
with the SECONDARY BUS NUMBER and SUBORDINATE BUS NUMBER registers of its
PCI-to-PCI bridges to determine if the configuration cycle is meant for the Primary PCI, or a
downstream PCI bus.
3.2.4 PCI Express Bus Configuration Mechanism
From the configuration perspective, the PCI Express ports are seen as PCI bus interfaces residing
on a Secondary Bus side of the “virtual” PCI-to-PCI bridges referred to as the MCH Host-to-PCI
Express bridges. On the Primary bus side, the “virtual” PCI-to-PCI bridge is attached to PCI Bus 0.
Therefore the PRIMARY BUS NUMBER register is hardwired to ‘0’. The “virtual” PCI-to-PCI
bridge entity converts Type 1 PCI Bus Configuration cycles on PCI Bus 0 into Type 0 or Type 1
configuration cycles on the PCI Express interfaces. Type 1 configuration cycles on PCI Bus 0 that
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