36 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
Figure 3-1. PCI Device Map
Processors
MCH
PCI Express Bridge
Bus 0, Dev 2
PCI Express Bridge
Bus 0, Dev 4
PCI Express Bridge
Bus 0, Dev 6
PCI Express Bridge
Bus 0, Dev 5
PCI Express Bridge
Bus 0, Dev 7
Hub
Interface
PCI Config Window in I/O Space
Intel
®
ICH5R
Hub
Interface
LPC Device
Bus 0, Dev 31, Func 0
IDE Controller
Bus 0, Dev 31, Func 1
S-ATA or RAID Controller
Bus 0, Dev 31, Func 2
AC97 Controller
Bus 0, Dev 31, Func 5,6
USB Controllers
Bus 0, Dev 29,
Func 0,1,2,3,7
HI-PCI Bridge
Bus 0, Dev 30, Func 0
LAN Controller
Bus n, Dev 8, Func 0
x8 or x4
PCI Express
Port A or A0
Primary PCI
Programmable
Bus #
Hub Interface (logical PCI Bus 0)
x8 or x4
PCI Express
Port B or B0
x8 or x4
PCI Express
Port C or C0
x4
PCI Express
Port A1
x4
PCI Express
Port B1
X4
PCI Express
Port C1
SMBus Controller
Bus 0, Dev 31, Func 3
Extended Configuration
Registers
Bus 0, Dev 8
Memory Controller Hub
Bus 0, Dev 0, Func 0
MCH Error Reporting
Bus 0, Dev 0, Func 1
DMA Controller
Bus 0, Dev 1
PCI Express Bridge
Bus 0, Dev 3