34 Intel
®
E7520 Memory Controller Hub (MCH) Datasheet
Register Descriptions
3.1.1 Platform Configuration
The MCH and the ICH are physically connected by the legacy Hub Interface (HI). From a
configuration standpoint, the HI is logically PCI bus 0. As a result, all devices internal to the MCH
and ICH appear to be on PCI bus 0. The system’s primary PCI expansion bus is physically attached
to the ICH and, from a configuration perspective, appears to be a hierarchical PCI bus behind a
PCI-to-PCI bridge and therefore has a programmable bus number.
The primary PCI bus is referred to in this document as PCI_A, and is not PCI bus 0 from a
configuration standpoint.
The PCI Express ports appear to system software as PCI buses behind PCI-to-PCI bridges that
reside as devices on PCI bus 0.
The MCH decodes multiple PCI device numbers. The configuration registers for the devices are
mapped as devices residing on PCI bus 0. Each device number may contain multiple functions.
The PCI predefined header has five fields that deal with device identification. All devices are
required to implement these fields. Generic configuration software will easily be able to identify
devices that are available for use. These registers are read-only. The five fields are Vendor ID,
Device ID, Revision ID, Header Type, and Class Code.
The 16-bit Vendor ID value assigned to Intel is 8086h.
The following table shows the device # assignment for the various internal MCH devices:
Reserved
Registers
Registers that are marked as “Reserved” must not be modified by system software. Reads to
“Reserved” registers may return non-zero values. Writes to “reserved” registers may cause
system failure.
Default
Value upon
Reset
Upon a Reset, the MCH sets its entire internal configuration registers to predetermined default
states. Some register values at reset are determined by external strapping options. A register's
default value represents the minimum functionality feature set required to successfully bring up
the system. Hence, it does not represent the optimal system configuration. It is the responsibility
of the system initialization software (usually BIOS) to properly determine the DRAM
configurations, operating parameters and optional system features that are applicable, and to
program the MCH registers accordingly.
Sticky
Registers
Certain registers in the MCH are sticky through a hard reset. They will only be reset on a Power
Good reset. These registers, in general, are the error logging registers and a few special cases.
The error command registers are not sticky, in order to avoid incorrect error reporting through a
mechanism that has not yet been set up in code. Only those registers that are explicitly marked
as such are sticky.
The Device 0, Function 1 error logging registers are sticky. The command registers are not.
Type Description
Table 3-1. PCI Device Number Assignment (Sheet 1 of 2)
MCH Function Device #, Function #
Memory Controller Hub (Hub Interface)
MCH Error Reporting (Hub Interface)
Device 0, Function 0
Device 0, Function 1
DMA Controller Device 1
Host-to-PCI Express A Bridge (x8 or x4) Device 2
Host-to-PCI Express A1 Bridge (x4 only) Device 3
Host-to-PCI Express B Bridge (x8 or x4) – (Supports Hot-Swap) Device 4
Host-to-PCI Express B1 Bridge (x4 only) Device 5